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SN74ALVCH373DW PDF预览

SN74ALVCH373DW

更新时间: 2024-09-28 23:09:43
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德州仪器 - TI 锁存器输出元件
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12页 213K
描述
OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

SN74ALVCH373DW 数据手册

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ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇꢈ ꢉꢂ ꢉ  
ꢊ ꢇꢋꢄꢅ ꢋ ꢌꢄꢁꢀ ꢍꢄꢌꢎ ꢁꢋ ꢏꢐꢋ ꢑꢍ ꢎ ꢅꢄꢋꢇ ꢈ  
ꢒ ꢓꢋ ꢈ ꢉ ꢐꢀꢋꢄꢋ ꢎ ꢊ ꢔꢋ ꢍꢔ ꢋꢀ  
SCES116G − JULY 1997 − REVISED AUGUST 2003  
DGV, DW, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
Operates From 1.65 V to 3.6 V  
Max t of 3.3 ns at 3.3 V  
pd  
24-mA Output Drive at 3.3 V  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
1
2
3
4
5
6
7
8
9
20  
19 8Q  
18 8D  
17 7D  
16 7Q  
15 6Q  
14 6D  
13 5D  
12 5Q  
11 LE  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
D
D
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
GND 10  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
This octal transparent D-type latch is designed for 1.65-V to 3.6-V V  
operation.  
CC  
The SN74ALVCH373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus  
drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs.  
When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors  
with the bus-hold circuitry is not recommended.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
Tube  
SN74ALVCH373DW  
SN74ALVCH373DWR  
SN74ALVCH373PWR  
SN74ALVCH373DGVR  
SN74ALVCH373GQNR  
SN74ALVCH373ZQNR  
SOIC − DW  
ALVCH373  
Tape and reel  
Tape and reel  
Tape and reel  
TSSOP − PW  
TVSOP − DGV  
VB373  
VB373  
−40°C to 85°C  
VFBGA − GQN  
Tape and reel  
VB373  
VFBGA − ZQN (Pb-free)  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢋꢠ  
Copyright 2003, Texas Instruments Incorporated  
ꢜ ꢠ ꢝ ꢜꢕ ꢖꢪ ꢘꢗ ꢛ ꢣꢣ ꢡꢛ ꢙ ꢛ ꢚ ꢠ ꢜ ꢠ ꢙ ꢝ ꢥ  
ꢞꢠ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74ALVCH373DW 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVCH373DWE4 TI

类似代替

ALVC/VCX/A SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, SOIC-20
SN74ALVCH373DWRE4 TI

类似代替

ALVC/VCX/A SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, SOIC-20
SN74ALVCH373DWR TI

类似代替

OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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SN74ALVCH373DWG4 TI

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SN74ALVCH373PW TI

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SN74ALVCH373ZQNR TI

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SN74ALVCH374_16 TI

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