SN74ALVCH32501GKE

更新时间： 2024-09-28 22:09:47

品牌	Logo	应用领域
德州仪器 - TI		总线收发器输出元件
页数	文件大小	规格书
11页	162K
描述
36-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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SN74ALVCH32501

36-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES144C – OCTOBER 1998 – REVISED MAY 2000

Member of the Texas Instruments

Widebus Family

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

EPIC (Enhanced-Performance Implanted

CMOS) Submicron Process

Latch-Up Performance Exceeds 250 mA Per

JESD 17

UBT (Universal Bus Transceiver)

Combines D-Type Latches and D-Type

Flip-Flops for Operation in Transparent,

Latched, or Clocked Mode

Packaged in Plastic Fine-Pitch Ball Grid

Array Package

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

description

This 36-bit universal bus transceiver is designed for 1.65-V to 3.6-V V

operation.

This device can be used as two 18-bit transceivers or one 36-bit transceiver. Data flow in each direction is

controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and

CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When

LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored

in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When

OEAB is low, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The output enables are

complementary (OEAB is active high and OEBA is active low).

To ensure the high-impedance state during power up or power down, OEBA should be tied to V

through a

pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor

is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH32501 is characterized for operation from –40°C to 85°C.

†

FUNCTION TABLE

INPUTS

OUTPUT

OEAB

LEAB

CLKAB

↑

‡

†

‡

A-to-B data flow is shown; B-to-A flow is similar but

uses OEBA, LEBA, and CLKBA.

Output level before the indicated steady-state input

conditions were established, provided that CLKAB

was high before LEAB went low

Output level before the indicated steady-state input

conditions were established

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC, UBT, and Widebus are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...11

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与SN74ALVCH32501GKE相关器件

型号	品牌	获取价格	描述	数据表
SN74ALVCH32501GKF	TI	获取价格	暂无描述
SN74ALVCH32501GKFR	TI	获取价格	ALVC/VCX/A SERIES, DUAL 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PBGA114, PLASTIC, LFBG
SN74ALVCH32501KR	TI	获取价格	36-Bit Universal Bus Transceiver with 3-State Outputs 114-BGA MICROSTAR -40 to 85
SN74ALVCH32973	TI	获取价格	16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH EIGHT INDEPENDENT BUFFERS
SN74ALVCH32973KR	TI	获取价格	16-BIT BUS TRANSCEIVER AND TRANSPARENT D-TYPE LATCH WITH EIGHT INDEPENDENT BUFFERS
SN74ALVCH373	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74ALVCH373DGV	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74ALVCH373DGVR	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74ALVCH373DW	TI	获取价格	OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74ALVCH373DWE4	TI	获取价格	ALVC/VCX/A SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, SOIC-20

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