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SN74ALVCH245PWRG4 PDF预览

SN74ALVCH245PWRG4

更新时间： 2024-09-16 05:29:35
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
14页 408K
描述
OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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SN74ALVCH245PWRG4 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP20,.25
针数：20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.18
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G20
JESD-609代码：e4长度：6.5 mm
逻辑集成电路类型：BUS TRANSCEIVER湿度敏感等级：1
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP20,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
传播延迟（tpd）：6 ns认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmBase Number Matches：1

SN74ALVCH245PWRG4 数据手册

 浏览型号SN74ALVCH245PWRG4的Datasheet PDF文件第2页浏览型号SN74ALVCH245PWRG4的Datasheet PDF文件第3页浏览型号SN74ALVCH245PWRG4的Datasheet PDF文件第4页浏览型号SN74ALVCH245PWRG4的Datasheet PDF文件第5页浏览型号SN74ALVCH245PWRG4的Datasheet PDF文件第6页浏览型号SN74ALVCH245PWRG4的Datasheet PDF文件第7页 
SN74ALVCH245  
OCTAL BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES119G–JULY 1997–REVISED SEPTEMBER 2004  
FEATURES  
DGV, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
•
•
•
•
Operates From 1.65 V to 3.6 V  
Max tpd of 3.4 ns at 3.3 V  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
DIR  
A1  
A2  
V
CC  
±24-mA Output Drive at 3.3 V  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
A3  
A4  
•
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
A5  
A6  
A7  
DESCRIPTION/ORDERING INFORMATION  
This octal bus transceiver is designed for 1.65-V to  
3.6-V VCC operation.  
A8  
GND  
The SN74ALVCH245 is designed for asynchronous  
communication between data buses. The device  
transmits data from the A bus to the B bus or from  
the B bus to the A bus, depending on the logic level  
at the direction-control (DIR) input. The output-enable  
(OE) input can be used to disable the device so the  
buses are effectively isolated.  
<br/>  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors  
with the bus-hold circuitry is not recommended.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74ALVCH245DW  
TOP-SIDE MARKING  
ALVCH245  
Tube  
SOIC - DW  
SOP - NS  
Tape and reel  
SN74ALVCH245DWR  
SN74ALVCH245NSR  
SN74ALVCH245PW  
SN74ALVCH245PWR  
SN74ALVCH245DGVR  
Tape and reel  
Tube  
ALVCH245  
VB245  
-40°C to 85°C  
TSSOP - PW  
TVSOP - DGV  
Tape and reel  
Tape and reel  
VB245  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
FUNCTION TABLE  
INPUTS  
OPERATION  
OE  
L
DIR  
L
B data to A bus  
A data to B bus  
Isolation  
L
H
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1997–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...14

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SN74ALVCH245PWRG4 替代型号

型号 品牌 替代类型 描述 数据表
74ALVC245PW,118 NXP

类似代替

 74ALVC245 - Octal bus transceiver; 3-state@en-us TSSOP2 20-Pin
SN74ALVCH245PWR TI

类似代替

 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
74ALVC245MTC FAIRCHILD

功能相似

 Low Voltage Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs

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