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SN74ALVCH245DGV

更新时间： 2024-11-20 23:09:43
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路电视光电二极管输出元件
页数 文件大小 规格书
8页 114K
描述
OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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SN74ALVCH245DGV 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：PLASTIC, TVSOP-20针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.48Is Samacsys：N
其他特性：WITH DIRECTION CONTROL系列：ALVC/VCX/A
JESD-30 代码：R-PDSO-G20长度：5 mm
逻辑集成电路类型：BUS TRANSCEIVER位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP20,.25,16
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）：6 ns认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.4 mm端子位置：DUAL
宽度：4.4 mmBase Number Matches：1

SN74ALVCH245DGV 数据手册

 浏览型号SN74ALVCH245DGV的Datasheet PDF文件第2页浏览型号SN74ALVCH245DGV的Datasheet PDF文件第3页浏览型号SN74ALVCH245DGV的Datasheet PDF文件第4页浏览型号SN74ALVCH245DGV的Datasheet PDF文件第5页浏览型号SN74ALVCH245DGV的Datasheet PDF文件第6页浏览型号SN74ALVCH245DGV的Datasheet PDF文件第7页 
SN74ALVCH245  
OCTAL BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCES119D – JULY 1997 – REVISED MAY 1999  
DGV, DW, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
DIR  
A1  
V
CC  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
A2  
A3  
A4  
Package Options Include Plastic  
Small-Outline (DW), Thin Very  
Small-Outline (DGV), and Thin Shrink  
Small-Outline (PW) Packages  
A5  
A6  
A7  
A8  
GND  
description  
This octal bus transceiver is designed for 1.65-V to 3.6-V V  
operation.  
CC  
The SN74ALVCH245 is designed for asynchronous communication between data buses. The device transmits  
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the  
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are  
effectively isolated.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH245 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OPERATION  
OE  
L
DIR  
L
B data to A bus  
A data to B bus  
Isolation  
L
H
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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