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SN74ALVCH16832

更新时间： 2024-11-16 23:09:43
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德州仪器 - TI 驱动器输出元件双倍数据速率
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9页 127K
描述
1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS

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SN74ALVCH16832 数据手册

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SN74ALVCH16832  
1-TO-4 ADDRESS REGISTER/DRIVER  
WITH 3-STATE OUTPUTS  
SCES098D – MAY 1997 – REVISED FEBRUARY 1999  
DGG PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
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51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
4Y1  
3Y1  
GND  
2Y1  
1Y2  
2Y2  
GND  
3Y2  
4Y2  
2
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
3
4
5
1Y1  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
6
V
V
CC  
A1  
CC  
7
1Y3  
2Y3  
GND  
3Y3  
4Y3  
GND  
8
GND  
A2  
GND  
A3  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
Packaged in Thin Shrink Small-Outline  
Package  
V
CC  
NC  
GND  
CLK  
OE1  
OE2  
SEL  
GND  
A4  
V
CC  
GND  
1Y4  
2Y4  
3Y4  
4Y4  
GND  
1Y5  
2Y5  
description  
This 1-bit to 4-bit address register/driver is  
designed for 1.65-V to 3.6-V V operation. This  
CC  
device is ideal for use in applications in which a  
single address bus is driving four separate  
memory locations. The SN74ALVCH16832 can  
be used as a buffer or a register, depending on the  
logic level of the select (SEL) input.  
A5  
V
V
CC  
CC  
WhenSELisalogichigh, thedeviceisinthebuffer  
mode. The outputs follow the inputs and are  
controlled by the two output-enable (OE) inputs.  
Each OE controls two groups of seven outputs.  
GND  
A6  
GND  
A7  
3Y5  
4Y5  
GND  
GND  
V
V
CC  
CC  
When SEL is a logic low, the device is in the  
register mode. The register is an edge-triggered  
D-type flip-flop. On the positive transition of the  
clock (CLK) input, data at the A inputs is stored in  
the internal registers. OE operates the same as in  
the buffer mode.  
4Y7  
3Y7  
GND  
2Y7  
1Y6  
2Y6  
GND  
3Y6  
4Y6  
1Y7  
WhenOE is a logic low, the outputs are in a normal  
logic state (high or low logic level). When OE is a  
logic high, the outputs are in the high-impedance  
state.  
NC – No internal connection  
Neither SEL nor OE affect the internal operation of the flip-flops. Old data can be retained or new data can be  
entered while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16832 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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