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SN74ALVCH16831

更新时间： 2024-11-03 23:09:43
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德州仪器 - TI 驱动器输出元件双倍数据速率
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9页 127K
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1-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS

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SN74ALVCH16831 数据手册

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SN74ALVCH16831  
1-TO-4 ADDRESS REGISTER/DRIVER  
WITH 3-STATE OUTPUTS  
SCES083D – AUGUST 1996 – REVISED FEBRUARY 1999  
DBB PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
4Y1  
3Y1  
GND  
2Y1  
1Y2  
2Y2  
GND  
3Y2  
4Y2  
1
80  
79  
78  
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41  
2
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
3
4
1Y1  
5
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
V
V
6
CC  
CC  
NC  
A1  
GND  
NC  
A2  
GND  
NC  
1Y3  
2Y3  
GND  
3Y3  
4Y3  
GND  
1Y4  
2Y4  
7
8
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
9
10  
11  
12  
13  
14  
15  
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17  
18  
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34  
35  
36  
37  
38  
39  
40  
Packaged in Thin Very Small-Outline  
Package  
A3  
description  
V
V
CC  
CC  
This 1-bit to 4-bit address register/driver is  
designed for 1.65-V to 3.6-V V operation. The  
NC  
A4  
3Y4  
4Y4  
GND  
1Y5  
2Y5  
3Y5  
4Y5  
GND  
1Y6  
2Y6  
CC  
device is ideal for use in applications in which a  
single address bus is driving four separate  
memory locations. The SN74ALVCH16831 can  
be used as a buffer or a register, depending on the  
logic level of the select (SEL) input.  
GND  
CLK  
OE1  
OE2  
SEL  
GND  
A5  
When SEL is logic high, the device is in the buffer  
mode. The outputs follow the inputs and are  
controlled by the two output-enable (OE) controls.  
Each OE controls two groups of nine outputs.  
A6  
V
V
CC  
CC  
A7  
NC  
GND  
A8  
NC  
GND  
A9  
3Y6  
4Y6  
GND  
1Y7  
2Y7  
GND  
3Y7  
4Y7  
When SEL is logic low, the device is in the register  
mode. The register is an edge-triggered D-type  
flip-flop. On the positive transition of the clock  
(CLK) input, data set up at the A inputs is stored  
in the internal registers. OE controls operate the  
same as in buffer mode.  
When OE is logic low, the outputs are in a normal  
logic state (high or low logic level). When OE is  
logic high, the outputs are in the high-impedance  
state.  
NC  
V
V
CC  
CC  
4Y9  
3Y9  
GND  
2Y9  
1Y8  
2Y8  
GND  
3Y8  
4Y8  
SEL and OE do not affect the internal operation of  
the flip-flops. Old data can be retained or new data  
can be entered while the outputs are in the  
high-impedance state.  
1Y9  
NC – No internal connection  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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