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SN74ALVCH16827-EP PDF预览

SN74ALVCH16827-EP

更新时间： 2024-09-16 12:22:03
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德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
12页 286K
描述
20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS

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SN74ALVCH16827-EP 数据手册

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SN74ALVCH16827-EP  
20-BIT BUFFER/DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES676–SEPTEMBER 2006  
FEATURES  
DGG OR DL PACKAGE  
(TOP VIEW)  
•
Controlled Baseline  
– One Assembly/Test Site, One Fabrication  
Site  
1
56  
55  
54  
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42  
41  
40  
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38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1OE1  
1Y1  
1OE2  
1A1  
2
•
•
Extended Temperature Performance of –55°C  
to 125°C  
3
1Y2  
GND  
1Y3  
1A2  
GND  
1A3  
4
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
5
6
1Y4  
1A4  
•
•
•
Enhanced Product-Change Notification  
7
V
CC  
V
CC  
(1)  
Qualification Pedigree  
8
1Y5  
1Y6  
1Y7  
GND  
1Y8  
1Y9  
1Y10  
2Y1  
2Y2  
2Y3  
GND  
2Y4  
2Y5  
2Y6  
1A5  
1A6  
1A7  
GND  
1A8  
1A9  
1A10  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
9
Member of the Texas Instruments Widebus™  
Family  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
•
•
EPIC™ (Enhanced-Performance Implanted  
CMOS) Submicron Process  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
•
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
V
CC  
V
CC  
2Y7  
2Y8  
2A7  
2A8  
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
GND  
2Y9  
2Y10  
2OE1  
GND  
2A9  
2A10  
2OE2  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
DESCRIPTION  
This 20-bit noninverting buffer/driver is designed for 1.65-V to 3.6-V VCC operation.  
The SN74ALVCH16827 is composed of two 10-bit sections with separate output-enable signals. For either 10-bit  
buffer section, the two output-enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be low for the  
corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer  
section are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
–55°C to 125°C  
SSOP – DL  
Tape and reel  
CALVCH16827MDLREP  
ALVCH16827EP  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, EPIC are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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