5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SN74ALVCH16646
SN74ALVCH16646 PDF预览

SN74ALVCH16646

更新时间： 2024-11-05 23:09:43
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
12页 189K
描述
16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SN74ALVCH16646 数据手册

 浏览型号SN74ALVCH16646的Datasheet PDF文件第2页浏览型号SN74ALVCH16646的Datasheet PDF文件第3页浏览型号SN74ALVCH16646的Datasheet PDF文件第4页浏览型号SN74ALVCH16646的Datasheet PDF文件第5页浏览型号SN74ALVCH16646的Datasheet PDF文件第6页浏览型号SN74ALVCH16646的Datasheet PDF文件第7页 
SN74ALVCH16646  
16-BIT BUS TRANSCEIVER AND REGISTER  
WITH 3-STATE OUTPUTS  
SCES032E– JULY 1995 – REVISED FEBRUARY 1999  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1DIR  
1CLKAB  
1SAB  
GND  
1OE  
2
1CLKBA  
1SBA  
GND  
1B1  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
3
4
5
1A1  
1A2  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
6
1B2  
7
V
V
CC  
CC  
8
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), and Thin Very  
Small-Outline (DGV) Packages  
description  
This 16-bit bus transceiver and register is  
designed for 1.65-V to 3.6-V V operation.  
CC  
The SN74ALVCH16646 can be used as two 8-bit  
transceivers or one 16-bit transceiver. Data on the  
A or B bus is clocked into the registers on the  
low-to-high transition of the appropriate clock  
(CLKAB or CLKBA) input. Figure 1 illustrates the  
four fundamental bus-management functions that  
can be performed with the SN74ALVCH16646.  
V
V
CC  
CC  
2A7  
2A8  
GND  
2B7  
2B8  
GND  
2SBA  
2CLKBA  
2OE  
2SAB  
2CLKAB  
2DIR  
Output-enable (OE) and direction-control (DIR)  
inputs are provided to control the transceiver  
functions. Inthetransceivermode, datapresentat  
the high-impedance port may be stored in either  
register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent  
mode)data. Thecircuitryusedforselectcontroleliminatesthetypicaldecodingglitchthatoccursinamultiplexer  
during the transition between stored and real-time data. DIR determines which bus receives data when OE is  
low. In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the  
other register.  
When an output function is disabled, the input function is still enabled and may be used to store and transmit  
data. Only one of the two buses, A or B, can be driven at a time.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16646 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

下载PDF

与SN74ALVCH16646相关器件

型号 品牌 获取价格 描述 数据表
SN74ALVCH16646DGG TI

获取价格

 		16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SN74ALVCH16646DGGR TI

获取价格

 		暂无描述
SN74ALVCH16646DGV TI

获取价格

 		16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SN74ALVCH16646DGVR TI

获取价格

 		具有三态输出的 16 位总线收发器和寄存器 | DGV | 56 | -40 to 85
SN74ALVCH16646DL TI

获取价格

 		16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SN74ALVCH16646DLR TI

获取价格

 		16-Bit Bus Transceiver And Register With 3-State Outputs 56-SSOP -40 to 85
SN74ALVCH16652DGGR TI

获取价格

 		ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP-
SN74ALVCH16652DL TI

获取价格

 		ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, PLA
SN74ALVCH16721 TI

获取价格

 		3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
SN74ALVCH16721DGG TI

获取价格

 		3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

与SN74ALVCH16646相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证