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SN74ALVCH16601DL PDF预览

SN74ALVCH16601DL

更新时间： 2024-11-08 23:09:43
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
10页 144K
描述
18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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中文翻译

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SN74ALVCH16601DL 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SSOP
包装说明：SSOP, SSOP56,.4针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.37其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; WITH CLOCK ENABLE
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：18.41 mm
负载电容（CL）：50 pF逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.024 A湿度敏感等级：1
位数：18功能数量：1
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP56,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH包装方法：TUBE
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：0.04 mAProp。Delay @ Nom-Sup：4.1 ns
传播延迟（tpd）：5.8 ns认证状态：Not Qualified
座面最大高度：2.79 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：7.49 mm
Base Number Matches：1

SN74ALVCH16601DL 数据手册

 浏览型号SN74ALVCH16601DL的Datasheet PDF文件第2页浏览型号SN74ALVCH16601DL的Datasheet PDF文件第3页浏览型号SN74ALVCH16601DL的Datasheet PDF文件第4页浏览型号SN74ALVCH16601DL的Datasheet PDF文件第5页浏览型号SN74ALVCH16601DL的Datasheet PDF文件第6页浏览型号SN74ALVCH16601DL的Datasheet PDF文件第7页 
SN74ALVCH16601  
18-BIT UNIVERSAL BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCES027E – JULY 1995 – REVISED MAY 2000  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
UBT (Universal Bus Transceiver)  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
OEAB  
LEAB  
A1  
GND  
A2  
CLKENAB  
CLKAB  
B1  
GND  
B2  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, Clocked, or Clock-Enabled Mode  
2
3
4
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
5
6
A3  
B3  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
7
V
V
CC  
A4  
CC  
8
B4  
B5  
B6  
GND  
B7  
9
A5  
A6  
GND  
A7  
A8  
A9  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
B8  
B9  
B10  
B11  
B12  
GND  
B13  
B14  
B15  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
description  
This 18-bit universal bus transceiver is designed  
for 1.65-V to 3.6-V V operation.  
CC  
V
V
CC  
CC  
A16  
A17  
GND  
A18  
OEBA  
LEBA  
B16  
B17  
GND  
B18  
CLKBA  
CLKENBA  
The SN74ALVCH16601 combines D-type latches  
and D-type flip-flops to allow data flow in  
transparent, latched, and clocked modes.  
Data flow in each direction is controlled by  
output-enable (OEAB and OEBA), latch-enable  
(LEAB and LEBA), and clock (CLKAB and  
CLKBA)inputs. The clock can be controlled by the  
clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent  
mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level.  
If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable  
OEAB is active low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the  
high-impedance state.  
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16601 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC, UBT, and Widebus are trademarks of Texas Instruments.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

中文翻译

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SN74ALVCH16601DL 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVCH16601DLR TI

完全替代

 18-bit universal bus transceiver with 3-state outputs 56-SSOP -40 to 85

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 		16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
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SN74ALVCH16646DL TI

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 		16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SN74ALVCH16646DLR TI

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 		16-Bit Bus Transceiver And Register With 3-State Outputs 56-SSOP -40 to 85
SN74ALVCH16652DGGR TI

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