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SN74ALVCH16525DGGR PDF预览

SN74ALVCH16525DGGR

更新时间： 2024-11-05 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
10页 155K
描述
ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, TSSOP-56

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SN74ALVCH16525DGGR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP56,.3,20针数：56
Reach Compliance Code：unknownHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.81
其他特性：WITH CLOCK ENABLE FOR EACH REGISTER控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：ALVC/VCX/A
JESD-30 代码：R-PDSO-G56JESD-609代码：e4
长度：14 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.024 A湿度敏感等级：1
位数：18功能数量：1
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP56,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：3.3 V
Prop。Delay @ Nom-Sup：4.2 ns传播延迟（tpd）：4.5 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A触发器类型：POSITIVE EDGE
宽度：6.1 mmBase Number Matches：1

SN74ALVCH16525DGGR 数据手册

 浏览型号SN74ALVCH16525DGGR的Datasheet PDF文件第2页浏览型号SN74ALVCH16525DGGR的Datasheet PDF文件第3页浏览型号SN74ALVCH16525DGGR的Datasheet PDF文件第4页浏览型号SN74ALVCH16525DGGR的Datasheet PDF文件第5页浏览型号SN74ALVCH16525DGGR的Datasheet PDF文件第6页浏览型号SN74ALVCH16525DGGR的Datasheet PDF文件第7页 
SN74ALVCH16525  
18-BIT REGISTERED BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCES059D – NOVEMBER 1995 – REVISED SEPTEMBER 1999  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
CLKENAB  
OEAB  
A1  
SEL  
CLKAB  
B1  
GND  
B2  
2
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
3
4
GND  
A2  
A3  
5
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
6
B3  
7
V
V
CC  
A4  
CC  
8
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
B4  
B5  
B6  
GND  
B7  
9
A5  
A6  
GND  
A7  
A8  
A9  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Package Option Includes Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
B8  
B9  
B10  
B11  
B12  
GND  
B13  
B14  
B15  
description  
This 18-bit universal bus transceiver is designed  
for 1.65-V to 3.6-V V operation.  
CC  
Data flow in each direction is controlled by  
output-enable (OEAB and OEBA) and  
clock-enable (CLKENAB and CLKENBA) inputs.  
For the A-to-B data flow, the data flows through a  
single register. The B-to-A data can flow through  
a four-stage pipeline register path, or through a  
single register path, depending on the state of the  
select (SEL) input.  
V
V
CC  
CC  
A16  
A17  
GND  
A18  
B16  
B17  
GND  
B18  
CLK1BA  
CLK2BA  
OEBA  
CLKENBA  
Data is stored in the internal registers on the  
low-to-high transition of the clock (CLK) input,  
provided that the appropriate CLKEN inputs are  
low. The A-to-B data transfer is synchronized to  
the CLKAB input, and B-to-A data transfer is  
synchronized with the CLK1BA and CLK2BA  
inputs.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16525 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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SN74ALVCH16525DL TI

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 		18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74ALVCH16525DLR TI

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 		ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, GREEN,
SN74ALVCH16525GR TI

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 		ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, PLASTIC
SN74ALVCH16525GRGR TI

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 		ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, PLASTIC
SN74ALVCH16540DGG TI

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 		ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, INVERTED OUTPUT, PDSO48
SN74ALVCH16540DGGR TI

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 		ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, INVERTED OUTPUT, PDSO48, TSSOP-48
SN74ALVCH16540DL TI

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 		ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, INVERTED OUTPUT, PDSO48, 0.300 INCH, PLASTIC, SSOP-4
SN74ALVCH16540DLR TI

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 		ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, INVERTED OUTPUT, PDSO48, 0.300 INCH, PLASTIC, SSOP-4
SN74ALVCH16541DGG TI

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 		ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48
SN74ALVCH16541DGGR TI

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 		ALVC/VCX/A SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, PLASTIC, TSSOP-48

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