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SN74ALVCH16524 PDF预览

SN74ALVCH16524

更新时间： 2024-11-04 23:09:43
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
9页 127K
描述
18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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SN74ALVCH16524 数据手册

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SN74ALVCH16524  
18-BIT REGISTERED BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCES080C – JULY 1996 – REVISED FEBRUARY 1999  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
GND  
OEAB  
A1  
GND  
A2  
GND  
SEL  
B1  
GND  
B2  
1
2
3
4
5
6
7
8
9
56  
55  
54  
53  
52  
51  
50  
49  
48  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
A3  
B3  
V
V
CC  
CC  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
A4  
A5  
B4  
B5  
A6 10  
47 B6  
GND  
A7  
GND  
B7  
11  
12  
46  
45  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
A8 13  
A9 14  
44 B8  
43 B9  
description  
A10 15  
A11 16  
A12 17  
GND 18  
A13 19  
A14 20  
A15 21  
B10  
42  
41 B11  
40 B12  
39 GND  
38 B13  
37 B14  
36 B15  
This 18-bit universal bus transceiver is designed  
for 1.65-V to 3.6-V V operation.  
CC  
Data flow in each direction is controlled by  
output-enable (OEAB and OEBA) and  
clock-enable (CLKENBA) inputs. For the A-to-B  
data flow, the data flows through a single buffer.  
The B-to-A data can flow through a four-stage  
pipeline register path, or through a single register  
path, depending on the state of the select (SEL)  
input.  
V
22  
35  
V
CC  
CC  
A16 23  
A17 24  
34 B16  
33 B17  
32 GND  
31 B18  
30 CLK  
29 GND  
GND 25  
A18 26  
OEBA 27  
CLKENBA 28  
Data is stored in the internal registers on the  
low-to-high transition of the clock (CLK) input,  
provided that the appropriate CLKENBA input is  
low. The B-to-A data transfer is synchronized with  
CLK.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16524 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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