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SN74ALVCH162836DL

更新时间： 2024-11-17 22:36:15
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
10页 140K
描述
20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

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SN74ALVCH162836DL 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：SSOP包装说明：GREEN, PLASTIC, SSOP-56
针数：56Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：7.93
Is Samacsys：N控制类型：ENABLE LOW
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：18.415 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.012 A湿度敏感等级：1
位数：20功能数量：1
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP56,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3 VProp。Delay @ Nom-Sup：4 ns
传播延迟（tpd）：5.5 ns认证状态：Not Qualified
座面最大高度：2.79 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.49 mm
Base Number Matches：1

SN74ALVCH162836DL 数据手册

 浏览型号SN74ALVCH162836DL的Datasheet PDF文件第2页浏览型号SN74ALVCH162836DL的Datasheet PDF文件第3页浏览型号SN74ALVCH162836DL的Datasheet PDF文件第4页浏览型号SN74ALVCH162836DL的Datasheet PDF文件第5页浏览型号SN74ALVCH162836DL的Datasheet PDF文件第6页浏览型号SN74ALVCH162836DL的Datasheet PDF文件第7页 
SN74ALVCH162836  
20-BIT UNIVERSAL BUS DRIVER  
WITH 3-STATE OUTPUTS  
SCES122E – JULY 1997 – REVISED JUNE 1999  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
OE  
Y1  
Y2  
GND  
Y3  
Y4  
1
2
3
4
5
6
7
8
9
10  
56 CLK  
55 A1  
54 A2  
53 GND  
52 A3  
51 A4  
Output Port Has Equivalent 26-Ω Series  
Resistors, So No External Resistors Are  
Required  
Designed to Comply With JEDEC 168-Pin  
and 200-Pin SDRAM Buffered DIMM  
Specification  
V
50  
V
CC  
Y5  
CC  
49 A5  
48 A6  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
Y6  
Y7  
GND 11  
Y8 12  
47  
A7  
46 GND  
45 A8  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
Y9  
Y10  
Y11  
Y12  
Y13  
GND  
Y14  
Y15  
Y16  
A9  
A10  
A11  
A12  
A13  
GND  
A14  
A15  
A16  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Package Options Include Plastic Shrink  
Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), and Thin Very  
Small-Outline (DGV) Packages  
NOTE: For tape and reel order entry:  
V
V
The DGGR package is abbreviated to GR, and  
the DGVR package is abbreviated to VR.  
CC  
CC  
Y17  
Y18  
GND  
Y19  
Y20  
NC  
A17  
A18  
GND  
A19  
A20  
LE  
description  
This 20-bit universal bus driver is designed for  
1.65-V to 3.6-V V  
operation.  
CC  
Data flow from A to Y is controlled by the  
output-enable (OE) input. The device operates in  
the transparent mode when the latch-enable (LE)  
input is low. When LE is high, the A data is latched  
if the clock (CLK) input is held at a high or low logic  
level. If LE is high, the A data is stored in the  
latch/flip-flop on the low-to-high transition of CLK.  
When OE is high, the outputs are in the  
high-impedance state.  
NC – No internal connection  
The output port includes equivalent 26-Ω series resistors to reduce overshoot and undershoot.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH162836 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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 		ALVC/VCX/A SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO56, GREEN, PLASTIC, SSOP-56
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 		20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74ALVCH162841DGG TI

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 		20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74ALVCH162841DL TI

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 		20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74ALVCH162841DLR TI

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 		ALVC/VCX/A SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, GREEN, PLASTIC, SS
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 		具有三态输出的 9 位总线接口 D 类锁存器 | DGG | 56 | -40 to 85
SN74ALVCH16334 TI

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 		16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SN74ALVCH16334DGG TI

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 		16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

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