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SN74ALVCH162835DL

更新时间： 2024-11-17 23:09:43
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器输出元件
页数 文件大小 规格书
10页 138K
描述
18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

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SN74ALVCH162835DL 数据手册

 浏览型号SN74ALVCH162835DL的Datasheet PDF文件第2页浏览型号SN74ALVCH162835DL的Datasheet PDF文件第3页浏览型号SN74ALVCH162835DL的Datasheet PDF文件第4页浏览型号SN74ALVCH162835DL的Datasheet PDF文件第5页浏览型号SN74ALVCH162835DL的Datasheet PDF文件第6页浏览型号SN74ALVCH162835DL的Datasheet PDF文件第7页 
SN74ALVCH162835  
18-BIT UNIVERSAL BUS DRIVER  
WITH 3-STATE OUTPUTS  
SCES121E – JULY 1997 – REVISED JUNE 1999  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
NC  
NC  
Y1  
GND  
Y2  
Y3  
GND  
NC  
A1  
GND  
A2  
A3  
2
Output Port Has Equivalent 26-Ω Series  
Resistors, So No External Resistors Are  
Required  
3
4
5
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
6
7
V
V
CC  
Y4  
CC  
8
A4  
A5  
A6  
GND  
A7  
9
Y5  
Y6  
GND  
Y7  
Y8  
Y9  
Y10  
Y11  
Y12  
GND  
Y13  
Y14  
Y15  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
A8  
A9  
Package Options Include Plastic Shrink  
Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), and Thin Very  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
Small-Outline (DGV) Packages  
NOTE: For tape and reel order entry:  
The DGGR package is abbreviated to GR, and  
the DGVR package is abbreviated to VR.  
description  
V
V
CC  
CC  
Y16  
Y17  
GND  
Y18  
OE  
A16  
A17  
GND  
A18  
CLK  
GND  
This 18-bit universal bus driver is designed for  
1.65-V to 3.6-V V  
operation.  
CC  
Data flow from A to Y is controlled by the  
output-enable (OE) input. The device operates in  
the transparent mode when the latch-enable (LE)  
input is high. When LE is low, the A data is latched  
if the clock (CLK) input is held at a high or low logic  
level. If LE is low, the A data is stored in the  
latch/flip-flop on the low-to-high transition of CLK.  
When OE is high, the outputs are in the  
high-impedance state.  
LE  
NC – No internal connection  
The output port includes equivalent 26-Ω series resistors to reduce overshoot and undershoot.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH162835 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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SN74ALVCH162836DGV TI

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SN74ALVCH162836DL TI

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SN74ALVCH162836DLR TI

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 		具有三态输出的 20 位通用总线驱动器 | DGG | 56 | -40 to 85
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