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SN74ALVCH162721DGG PDF预览

SN74ALVCH162721DGG

更新时间： 2024-11-04 23:09:43
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
9页 127K
描述
3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

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SN74ALVCH162721DGG 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP-56针数：56
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.2Is Samacsys：N
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：14 mm
逻辑集成电路类型：BUS DRIVER湿度敏感等级：1
位数：20功能数量：1
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260传播延迟（tpd）：6.7 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6.1 mm
Base Number Matches：1

SN74ALVCH162721DGG 数据手册

 浏览型号SN74ALVCH162721DGG的Datasheet PDF文件第2页浏览型号SN74ALVCH162721DGG的Datasheet PDF文件第3页浏览型号SN74ALVCH162721DGG的Datasheet PDF文件第4页浏览型号SN74ALVCH162721DGG的Datasheet PDF文件第5页浏览型号SN74ALVCH162721DGG的Datasheet PDF文件第6页浏览型号SN74ALVCH162721DGG的Datasheet PDF文件第7页 
SN74ALVCH162721  
3.3-V 20-BIT FLIP-FLOP  
WITH 3-STATE OUTPUTS  
SCES055E – DECEMBER 1995 – REVISED JUNE 1999  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
OE  
Q1  
Q2  
GND  
Q3  
Q4  
1
2
3
4
5
6
7
8
9
56 CLK  
55 D1  
54 D2  
53 GND  
52 D3  
51 D4  
Output Ports Have Equivalent 26-Ω Series  
Resistors, So No External Resistors Are  
Required  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
V
50  
V
CC  
CC  
Q5  
Q6  
Q7 10  
GND 11  
Q8 12  
49 D5  
48 D6  
47 D7  
46 GND  
45 D8  
44 D9  
43 D10  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Q9 13  
Q10 14  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
NOTE: For tape and reel order entry:  
15  
42  
Q11  
Q12 16  
Q13 17  
D11  
41 D12  
40 D13  
The DGGR package is abbreviated to GR.  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
GND  
Q14  
Q15  
Q16  
GND  
D14  
D15  
D16  
description  
This 20-bit flip-flop is designed for low-voltage  
V
V
CC  
CC  
1.65-V to 3.6-V V  
operation.  
CC  
Q17  
Q18  
GND  
Q19  
Q20  
NC  
D17  
D18  
GND  
D19  
D20  
The 20 flip-flops of the SN74ALVCH162721 are  
edge-triggered D-type flip-flops with qualified  
clock storage. On the positive transition of the  
clock (CLK) input, the device provides true data at  
the Q outputs if the clock-enable (CLKEN) input is  
low. If CLKEN is high, no data is stored.  
CLKEN  
A buffered output-enable (OE) input places the 20  
outputs in either a normal logic state (high or low  
level) or the high-impedance state. In the  
high-impedance state, the outputs neither load  
NC – No internal connection  
nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive  
bus lines without interface or pullup components. OE does not affect the internal operation of the flip-flops. Old  
data can be retained or new data can be entered while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot and  
undershoot.  
The SN74ALVCH162721 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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与SN74ALVCH162721DGG相关器件

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SN74ALVCH162721DL ROCHESTER

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SN74ALVCH162721DLR ROCHESTER

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SN74ALVCH162721DLR TI

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 		3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
SN74ALVCH162721GR TI

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SN74ALVCH16272DGGR ETC

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SN74ALVCH16272DL TI

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 		ALVC/VCX/A SERIES, 12 MULTIPLEXER AND DEMUX/DECODER, PDSO56, PLASTIC, SSOP-56
SN74ALVCH16272DLR TI

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 		ALVC/VCX/A SERIES, 12 MULTIPLEXER AND DEMUX/DECODER, PDSO56, PLASTIC, SSOP-56
SN74ALVCH16280DBBR TI

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 		ALVC/VCX/A SERIES, 16-BIT EXCHANGER, TRUE OUTPUT, PDSO80, TSSOP-80
SN74ALVCH16282 TI

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 		18-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

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