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SN74ALVCH162525

更新时间： 2024-11-17 23:09:43
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德州仪器 - TI 总线收发器输出元件
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11页 169K
描述
18-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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SN74ALVCH162525 数据手册

 浏览型号SN74ALVCH162525的Datasheet PDF文件第2页浏览型号SN74ALVCH162525的Datasheet PDF文件第3页浏览型号SN74ALVCH162525的Datasheet PDF文件第4页浏览型号SN74ALVCH162525的Datasheet PDF文件第5页浏览型号SN74ALVCH162525的Datasheet PDF文件第6页浏览型号SN74ALVCH162525的Datasheet PDF文件第7页 
SN74ALVCH162525  
18-BIT REGISTERED BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCES058F – NOVEMBER 1995 – REVISED SEPTEMBER 1999  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
CLKENAB  
OEAB  
A1  
SEL  
CLKAB  
B1  
GND  
B2  
2
B-Port Outputs Have Equivalent 26-Ω  
Series Resistors, So No External Resistors  
Are Required  
3
4
GND  
A2  
A3  
5
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
6
B3  
7
V
V
CC  
A4  
CC  
8
B4  
B5  
B6  
GND  
B7  
9
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
A5  
A6  
GND  
A7  
A8  
A9  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
B8  
B9  
Package Option Includes Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
B10  
B11  
B12  
GND  
B13  
B14  
B15  
NOTE: For tape and reel order entry:  
The DGGR package is abbreviated to GR.  
description  
This 18-bit universal bus transceiver is designed  
V
V
CC  
CC  
for 1.65-V to 3.6-V V  
operation.  
CC  
A16  
A17  
GND  
A18  
B16  
B17  
GND  
B18  
CLK1BA  
CLK2BA  
Data flow in each direction is controlled by  
output-enable (OEAB and OEBA) and  
clock-enable (CLKENAB and CLKENBA) inputs.  
For the A-to-B data flow, the data flows through a  
single register. The B-to-A data can flow through  
a four-stage pipeline register path, or through a  
single register path, depending on the state of the  
select (SEL) input.  
OEBA  
CLKENBA  
Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input, provided that the  
appropriate CLKEN inputs are low. The A-to-B data transfer is synchronized to the CLKAB input, and B-to-A  
data transfer is synchronized with the CLK1BA and CLK2BA inputs.  
The B outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot  
and undershoot.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH162525 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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