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SN74ALVCF162835

更新时间： 2024-11-17 23:09:43
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德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
12页 179K
描述
3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

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SN74ALVCF162835 数据手册

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SN74ALVCF162835  
3.3-V CMOS 18-BIT UNIVERSAL BUS DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES397A–JULY 2002–REVISED AUGUST 2004  
FEATURES  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
•
Member of the Texas Instruments Widebus™  
Family  
1
56  
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40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
NC  
NC  
GND  
NC  
•
•
•
•
•
•
Ideal for Use in PC133 Register DIMM  
Typical Output Skew . . . <250 ps  
VCC = 3.3 V ± 0.3 V . . . Normal Range  
VCC = 2.7 V to 3.6 V . . . Extended Range  
VCC = 2.5 V ± 0.2 V  
2
3
Y1  
GND  
Y2  
A1  
GND  
A2  
4
5
6
Y3  
A3  
7
V
CC  
V
CC  
Rail-to-Rail Output Swing for Increased Noise  
Margin  
8
Y4  
Y5  
Y6  
GND  
Y7  
Y8  
A4  
A5  
A6  
GND  
A7  
9
•
•
•
Balanced Output Drivers . . . ±18 mA  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Low Switching Noise  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
A8  
•
ESD Protection Exceeds JESD 22  
- 2000-V Human-Body Model (A114-A)  
- 200-V Machine Model (A115-A)  
Y9  
A9  
Y10  
Y11  
Y12  
GND  
Y13  
Y14  
Y15  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
- 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This 18-bit universal bus driver is designed for 2.3-V  
to 3.6-V VCC operation.  
V
CC  
V
CC  
Data flow from  
A to Y is controlled by the  
Y16  
Y17  
GND  
Y18  
OE  
A16  
A17  
GND  
A18  
CLK  
GND  
output-enable (OE) input. The device operates in the  
transparent mode when the latch-enable (LE) input is  
high. When LE is low, the A data is latched if the  
clock (CLK) input is held at a high or low logic level. If  
LE is low, the A data is stored in the latch/flip-flop on  
the low-to-high transition of CLK. When OE is high,  
the outputs are in the high-impedance state.  
LE  
NC − No internal connection  
The SN74ALVCF162835 has series damping  
resistors in the device output structure that reduce  
switching noise in 128-MB and 256-MB SDRAM  
modules. Designed with a drive capability of ±18 mA,  
this device is  
a
midway drive between the  
SN74ALVC162835 (±12 mA) and SN74ALVC16835  
(±24 mA).  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
Tube  
SN74ALVCF162835DL  
SN74ALVCF162835DLR  
SN74ALVCF162835GR  
SN74ALVCF162835VR  
SSOP - DL  
ALVCF162835  
Tape and reel  
Tape and reel  
Tape and reel  
-40°C to 85°C  
TSSOP - DGG  
TVSOP - DGV  
ALVCF162835  
VF2835  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2002–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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