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SN74ALVC32DGV

更新时间： 2024-11-24 22:39:55

品牌	Logo	应用领域
德州仪器 - TI		输入元件
页数	文件大小	规格书
9页	248K
描述
QUADRUPLE 2-INPUT POSITIVE-OR GATE

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数据手册

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SN74ALVC32DGV 数据手册

SN74ALVC32

QUADRUPLE 2-INPUT POSITIVE-OR GATE

www.ti.com

SCES108G–JULY 1997–REVISED NOVEMBER 2004

FEATURES

D, DGV, NS, OR PW PACKAGE

(TOP VIEW)

•

Operates From 1.65 V to 3.6 V

Max t_pdof 2.8 ns at 3.3 V

±24-mA Output Drive at 3.3 V

Latch-Up Performance Exceeds 250 mA Per

JESD 17

•

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

GND

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This quadruple 2-input positive-OR gate is designed for 1.65-V to 3.6-V V_CCoperation.

A B

The SN74ALVC32 performs the Boolean function Y =

or Y = A + B in positive logic.

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

ORDERABLE PART NUMBER

SN74ALVC32D

TOP-SIDE MARKING

Tube

SOIC - D

ALVC32

Tape and reel

Tube

SN74ALVC32DR

SN74ALVC32NSR

SN74ALVC32PW

SN74ALVC32PWR

SN74ALVC32DGVR

SOP - NS

ALVC32

VA32

-40°C to 85°C

TSSOP - PW

TVSOP - DGV

Tape and reel

VA32

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...9

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