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SN74ALVC16821

更新时间： 2024-09-16 12:22:31
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
11页 192K
描述
3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS

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SN74ALVC16821 数据手册

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SCAS269A − MARCH 1993 − REVISED AUGUST 1995  
DGG OR DL PACKAGE  
(TOP VIEW)  
D Member of the Texas Instruments  
WidebusFamily  
D EPIC (Enhanced-Performance Implanted  
D Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1CLK  
1D1  
1D2  
GND  
1D3  
1D4  
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CMOS) Submicron Process  
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D ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model (C = 200 pF,  
R = 0)  
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V
V
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CC  
CC  
1Q5  
1Q6  
1Q7  
GND  
1Q8  
1Q9  
1Q10  
2Q1  
2Q2  
2Q3  
GND  
2Q4  
2Q5  
2Q6  
1D5  
1D6  
1D7  
GND  
1D8  
1D9  
1D10  
2D1  
2D2  
2D3  
GND  
2D4  
2D5  
2D6  
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D Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
D Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
description  
This 20-bit bus-interface flip-flop is designed for  
low-voltage (3.3-V) V operation; it is tested at  
CC  
2.5-V, 2.7-V, and 3.3-V V  
.
CC  
The SN74ALVC16821 can be used as two 10-bit  
flip-flops or one 20-bit flip-flop. The 20 flip-flops  
are edge-triggered D-type flip-flops. On the  
positive transition of the clock (CLK) input, the  
device provides true data at the Q outputs.  
V
V
CC  
CC  
2Q7  
2Q8  
GND  
2Q9  
2Q10  
2OE  
2D7  
2D8  
GND  
2D9  
2D10  
2CLK  
A buffered output-enable (OE) input can be used  
to place the ten outputs in either a normal logic  
state (high or low level) or a high-impedance state.  
In the high-impedance state, the outputs neither  
load nor drive the bus lines significantly. The  
high-impedance state and increased drive  
provide the capability to drive bus lines without  
interface or pullup components.  
The output-enable (OE) input does not affect the internal operation of the flip-flops. Old data can be retained  
or new data can be entered while the outputs are in the high-impedance state.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVC16821 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)  
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the  
same printed-circuit-board area.  
The SN74ALVC16821 is characterized for operation from −40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
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Copyright 1995, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...11

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SN74ALVC16821 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVCH16821 TI

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