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SN74ALVC16721DL

更新时间： 2024-11-07 02:58:27
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
8页 137K
描述
3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

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SN74ALVC16721DL 数据手册

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SCAS267A − MARCH 1993 − REVISED MAY 1995  
DGG OR DL PACKAGE  
(TOP VIEW)  
D Member of the Texas Instruments  
WidebusFamily  
D EPIC (Enhanced-Performance Implanted  
D ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model (C = 200 pF,  
R = 0)  
OE  
Q1  
Q2  
GND  
Q3  
Q4  
1
2
3
4
5
6
7
8
9
10  
56 CLK  
55 D1  
54 D2  
53 GND  
52 D3  
51 D4  
CMOS) Submicron Process  
D Latch-Up Performance Exceeds 250 mA  
V
50  
V
CC  
CC  
Per JEDEC Standard JESD-17  
Q5  
Q6  
Q7  
GND 11  
Q8 12  
49 D5  
48 D6  
D Bus Hold On Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
47  
D7  
46 GND  
45 D8  
D Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
Q9  
Q10  
Q11  
Q12  
Q13  
GND  
Q14  
Q15  
Q16  
D9  
D10  
D11  
D12  
D13  
GND  
D14  
D15  
D16  
description  
This 20-bit flip-flop is designed specifically for  
low-voltage (3.3-V) V operation; it is tested at  
CC  
2.5-V, 2.7-V, and 3.3-V V  
.
CC  
The SN74ALVC16721’s 20 flip-flops are edge-  
triggered D-type flip-flops with qualified clock  
storage. On the positive transition of the clock  
(CLK) input, the device provides true data at the  
Q outputs if the clock-enable (CLKEN) input is low.  
If CLKEN is high, no data is stored.  
V
V
CC  
CC  
Q17  
Q18  
GND  
Q19  
Q20  
NC  
D17  
D18  
GND  
D19  
D20  
A buffered output-enable (OE) input places the  
20 outputs in either a normal logic state (high  
or low level) or a high-impedance state. In the  
high-impedance state, the outputs neither load  
CLKEN  
nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive  
bus lines without interface or pullup components. OE does not affect the internal operation of the flip-flops. Old  
data can be retained or new data can be entered while the outputs are in the high-impedance state.  
Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.  
The SN74ALVC16721 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)  
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the  
same printed-circuit-board area.  
The SN74ALVC16721 is characterized for operation from −40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
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Copyright 1995, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
12345678

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 		3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
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 		ALVC/VCX/A SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56
SN74ALVC16827DLR TI

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 		ALVC/VCX/A SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56
SN74ALVC16828 TI

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 		20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
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 		ALVC/VCX/A SERIES, DUAL 10-BIT DRIVER, INVERTED OUTPUT, PDSO56
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