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SN74ALVC16600DGG PDF预览

SN74ALVC16600DGG

更新时间： 2024-09-16 15:52:07
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
5页 73K
描述
ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56

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SN74ALVC16600DGG 技术参数

生命周期：Obsolete包装说明：TSSOP,
Reach Compliance Code：unknown风险等级：5.84
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; WITH CLOCK ENABLE系列：ALVC/VCX/A
JESD-30 代码：R-PDSO-G56长度：14 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER位数：18
功能数量：1端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
宽度：6.1 mmBase Number Matches：1

SN74ALVC16600DGG 数据手册

 浏览型号SN74ALVC16600DGG的Datasheet PDF文件第2页浏览型号SN74ALVC16600DGG的Datasheet PDF文件第3页浏览型号SN74ALVC16600DGG的Datasheet PDF文件第4页浏览型号SN74ALVC16600DGG的Datasheet PDF文件第5页 
SN74ALVC16600  
18-BIT UNIVERSAL BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCAS263A – JANUARY 1993 – REVISED MARCH 1994  
DGG OR DL PACKAGE  
(TOP VIEW)  
• Member of the Texas Instruments  
Widebus Family  
• UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, Clocked, or Clock-Enabled Mode  
OEAB  
LEAB  
A1  
GND  
A2  
CLKENAB  
CLKAB  
B1  
GND  
B2  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
2
3
4
• EPIC (Enhanced-Performance Implanted  
5
CMOS) Submicron Process  
A3  
B3  
6
• Designed to Facilitate Incident-Wave  
Switching for Line Impedances of 50 Ω  
or Greater  
V
V
7
CC  
CC  
A4  
A5  
A6  
GND  
A7  
B4  
B5  
B6  
GND  
B7  
8
9
• Typical V  
(Output Ground Bounce)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
OLP  
< 0.8 V at V  
= 3.3 V, T = 25°C  
CC  
A
• Typical V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
A8  
A9  
B8  
B9  
> 2 V at V  
= 3.3 V, T = 25°C  
A
• Bus-Hold On Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
B10  
B11  
B12  
GND  
B13  
B14  
B15  
• Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
description  
V
V
CC  
CC  
This 18-bit universal bus transceiver is designed  
for 2.7-V to 3.6-V V operation.  
A16 23  
A17 24  
34 B16  
33 B17  
CC  
GND 25  
A18 26  
32 GND  
31 B18  
The SN74ALVC16600 combines D-type latches  
and D-type flip-flops to allow data flow in  
transparent, latched, and clocked modes.  
OEBA 27  
LEBA 28  
30 CLKBA  
29 CLKENBA  
Data flow in each direction is controlled by  
output-enable (OEAB and OEBA), latch-enable  
(LEAB and LEBA), and clock (CLKAB and  
CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B  
data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is  
latched if CLKAB is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/flip-flop  
on the high-to-low transition of CLKAB. Output enable OEAB is active low. When OEAB is low, the outputs are  
active. When OEAB is high, the outputs are in the high-impedance state.  
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA, and CLKENBA.  
The SN74ALVC16600 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)  
packages,whichprovidetwicetheI/Opincountandfunctionalityofstandardsmall-outlinepackagesinthesame  
printed-circuit-board area.  
The SN74ALVC16600 is characterized for operation from –40°C to 85°C.  
EPIC, UBT, and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1994, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
9–1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345

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与SN74ALVC16600DGG相关器件

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 		ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
SN74ALVC16600DLR TI

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SN74ALVC16601DGGR TI

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SN74ALVC16646DGG TI

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SN74ALVC16646DGGR TI

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 		ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
SN74ALVC16646DL TI

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 		ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
SN74ALVC16646DLR TI

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 		ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
SN74ALVC16652DGGR TI

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 		ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
SN74ALVC16652DL TI

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 		ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
SN74ALVC16721 TI

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 		3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

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