5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SN74ALVC162601DLR
SN74ALVC162601DLR PDF预览

SN74ALVC162601DLR

更新时间： 2024-11-25 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
9页 140K
描述
18-Bit Universal Bus Transceiver With 3-State Outputs 56-SSOP -40 to 85

阅读下载

中文翻译

获取价格

SN74ALVC162601DLR 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：0.300 INCH, PLASTIC, SSOP-56针数：56
Reach Compliance Code：not_compliant风险等级：5.63
Is Samacsys：N其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; WITH CLOCK ENABLE
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
长度：18.415 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
位数：18功能数量：1
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP56,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
认证状态：Not Qualified座面最大高度：2.79 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：7.5 mm
Base Number Matches：1

SN74ALVC162601DLR 数据手册

 浏览型号SN74ALVC162601DLR的Datasheet PDF文件第2页浏览型号SN74ALVC162601DLR的Datasheet PDF文件第3页浏览型号SN74ALVC162601DLR的Datasheet PDF文件第4页浏览型号SN74ALVC162601DLR的Datasheet PDF文件第5页浏览型号SN74ALVC162601DLR的Datasheet PDF文件第6页浏览型号SN74ALVC162601DLR的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇꢈ ꢉꢊ ꢉꢋ ꢈ  
ꢈ ꢌ ꢍꢎꢏ ꢐꢑ ꢒꢁꢏ ꢆꢓꢔꢀ ꢄꢅꢑꢎ ꢒꢀꢑ ꢐꢔꢄ ꢁꢀ ꢇ ꢓꢏ ꢆ ꢓꢔ  
ꢕ ꢏꢐ ꢖꢑ ꢗ ꢍꢀꢐꢄꢐ ꢓꢑ ꢘꢒ ꢐꢙ ꢒꢐ ꢀ  
SCAS376 − MARCH 1994  
DGG OR DL PACKAGE  
(TOP VIEW)  
• Member of the Texas Instruments  
WidebusFamily  
• UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, Clocked, or Clock-Enabled Mode  
OEAB  
LEAB  
A1  
GND  
A2  
CLKENAB  
1
2
3
4
5
6
7
8
9
56  
55 CLKAB  
54 B1  
53 GND  
52 B2  
• EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
A3  
51 B3  
• Bus-Hold Data Inputs Eliminate the Need  
V
50  
V
CC  
A4  
CC  
for External Pullup Resistors on All I/O Pins  
49 B4  
• Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
A5  
48 B5  
A6 10  
47 B6  
GND 11  
A7 12  
46 GND  
45 B7  
description  
A8 13  
44 B8  
A9 14  
43 B9  
This 18-bit universal bus transceiver is designed  
for 2.7-V to 3.6-V V operation.  
A10 15  
A11 16  
A12 17  
GND 18  
A13 19  
A14 20  
A15 21  
42 B10  
41 B11  
40 B12  
39 GND  
38 B13  
37 B14  
36 B15  
CC  
The SN74ALVC162601 combines D-type latches  
and D-type flip-flops to allow data flow in  
transparent, latched, and clocked modes.  
Data flow in each direction is controlled by  
output-enable (OEAB and OEBA), latch-enable  
(LEAB and LEBA), and clock (CLKAB and  
CLKBA) inputs. The clock can be controlled by the  
clock-enable (CLKENAB and CLKENBA) inputs.  
For A-to-B data flow, the device operates in the  
transparent mode when LEAB is high. When  
LEAB is low, the A data is latched if CLKAB is held  
at a high or low logic level. If LEAB is low, the A-bus  
data is stored in the latch/flip-flop on the  
high-to-low transition of CLKAB. Output enable  
OEAB is active low. When OEAB is low, the  
outputs are active. When OEAB is high, the  
outputs are in the high-impedance state.  
V
22  
35  
V
CC  
CC  
A16 23  
A17 24  
GND 25  
A18 26  
OEBA 27  
LEBA 28  
34 B16  
33 B17  
32 GND  
31 B18  
30 CLKBA  
29 CLKENBA  
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA, and CLKENBA.  
The B-port outputs, include 25-Ω series resistors to reduce overshoot and undershoot.  
The SN74ALVC162601 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)  
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same  
printed-circuit-board area.  
The SN74ALVC162601 is characterized for operation from −40°C to 85°C.  
EPIC, UBT, and Widebus are trademarks of Texas Instruments Incorporated.  
ꢙ
ꢔ
ꢘ
ꢚ
ꢒ
ꢇ
ꢐ
ꢙ
ꢔ
ꢓ
ꢆ
ꢏ
ꢓ
ꢕ
ꢛ
ꢜ
ꢝ
ꢞ
ꢟ
ꢠ
ꢡ
ꢢ
ꢛ
ꢞ
ꢜ
ꢣ
ꢞ
ꢜ
ꢣ
ꢤ
ꢟ
ꢜ
ꢥ
ꢦ
ꢟ
ꢞ
ꢧ
ꢨ
ꢧꢤ ꢥ ꢛ ꢫꢜ ꢦꢩ ꢡ ꢥ ꢤ ꢞꢝ ꢧꢤ ꢪ ꢤ ꢬꢞ ꢦꢠꢤ ꢜꢢꢭ ꢇ ꢩꢡ ꢟꢡ ꢣꢢ ꢤꢟ ꢛꢥ ꢢꢛ ꢣ ꢧꢡ ꢢꢡ ꢡꢜ ꢧ ꢞꢢ ꢩꢤꢟ  
ꢣ
ꢢ
ꢥ
ꢛ
ꢜ
ꢢ
ꢩ
ꢤ
ꢝ
ꢞ
ꢟ
ꢠ
ꢡ
ꢢ
ꢛ
ꢪ
ꢤ
ꢞ
ꢟ
Copyright 1994, Texas Instruments Incorporated  
ꢥ
ꢦ
ꢤ
ꢣ
ꢛ
ꢝ
ꢛ
ꢣ
ꢡ
ꢢ
ꢛ
ꢞ
ꢜ
ꢥ
ꢡ
ꢟ
ꢤ
ꢧ
ꢤ
ꢥ
ꢛ
ꢫ
ꢜ
ꢫ
ꢞ
ꢡ
ꢬ
ꢥ
ꢭ
ꢐ
ꢤ
ꢮ
ꢡ
ꢥ
ꢏ
ꢜ
ꢥ
ꢢ
ꢟ
ꢨ
ꢠ
ꢣ ꢩꢡ ꢜ ꢫꢤ ꢞꢟ ꢧꢛ ꢥ ꢣ ꢞꢜ ꢢꢛ ꢜꢨꢤ ꢢ ꢩꢤ ꢥ ꢤ ꢦꢟ ꢞꢧ ꢨꢣꢢ ꢥ ꢯ ꢛꢢꢩ ꢞꢨꢢ ꢜꢞꢢ ꢛꢣꢤ ꢭ  
ꢤ
ꢜ
ꢢ
ꢥ
ꢟ
ꢤ
ꢥ
ꢤ
ꢟ
ꢪ
ꢤ
ꢥ
ꢢ
ꢩ
ꢤ
ꢟ
ꢛ
ꢫ
ꢩ
ꢢ
ꢢ
ꢞ
9−1  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...9

中文翻译

下载PDF

与SN74ALVC162601DLR相关器件

型号 品牌 获取价格 描述 数据表
SN74ALVC16260DGG TI

获取价格

 		ALVC/VCX/A SERIES, 12 MULTIPLEXER AND DEMUX/DECODER, PDSO56, TSSOP-56
SN74ALVC16260DGGR ETC

获取价格

 		Bus Exchanger
SN74ALVC16260DL TI

获取价格

 		12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74ALVC16260DLR TI

获取价格

 		暂无描述
SN74ALVC16269 TI

获取价格

 		12-BIT TO 24-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74ALVC16269DGG TI

获取价格

 		ALVC/VCX/A SERIES, 12-BIT EXCHANGER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP-56
SN74ALVC16269DGGR ETC

获取价格

 		Bus Exchanger
SN74ALVC16269DL TI

获取价格

 		12-BIT TO 24-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74ALVC16269DLR TI

获取价格

 		12-Bit To 24-Bit Registered Bus Transceiver With 3-State Outputs SN74ALVC16269 56-SSOP -40
SN74ALVC16270 TI

获取价格

 		12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS

与SN74ALVC162601DLR相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证