Datasheet > 逻辑 > 总线驱动器/收发器> SN74ALVC162601

SN74ALVC162601

更新时间： 2024-11-21 11:58:39

品牌	Logo	应用领域
德州仪器 - TI		总线收发器输出元件
页数	文件大小	规格书
9页	140K
描述
18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

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SN74ALVC162601 数据手册

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SCAS376 − MARCH 1994

DGG OR DL PACKAGE

(TOP VIEW)

• Member of the Texas Instruments

Widebus Family

• UBT  (Universal Bus Transceiver)

Combines D-Type Latches and D-Type

Flip-Flops for Operation in Transparent,

Latched, Clocked, or Clock-Enabled Mode

OEAB

LEAB

GND

CLKENAB

55 CLKAB

54 B1

53 GND

52 B2

• EPIC  (Enhanced-Performance Implanted

CMOS) Submicron Process

51 B3

• Bus-Hold Data Inputs Eliminate the Need

for External Pullup Resistors on All I/O Pins

49 B4

• Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

48 B5

A6 10

47 B6

GND 11

A7 12

46 GND

45 B7

description

A8 13

44 B8

A9 14

43 B9

This 18-bit universal bus transceiver is designed

for 2.7-V to 3.6-V V operation.

A10 15

A11 16

A12 17

GND 18

A13 19

A14 20

A15 21

42 B10

41 B11

40 B12

39 GND

38 B13

37 B14

36 B15

The SN74ALVC162601 combines D-type latches

and D-type flip-flops to allow data flow in

transparent, latched, and clocked modes.

Data flow in each direction is controlled by

output-enable (OEAB and OEBA), latch-enable

(LEAB and LEBA), and clock (CLKAB and

CLKBA) inputs. The clock can be controlled by the

clock-enable (CLKENAB and CLKENBA) inputs.

For A-to-B data flow, the device operates in the

transparent mode when LEAB is high. When

LEAB is low, the A data is latched if CLKAB is held

at a high or low logic level. If LEAB is low, the A-bus

data is stored in the latch/flip-flop on the

high-to-low transition of CLKAB. Output enable

OEAB is active low. When OEAB is low, the

outputs are active. When OEAB is high, the

outputs are in the high-impedance state.

A16 23

A17 24

GND 25

A18 26

OEBA 27

LEBA 28

34 B16

33 B17

32 GND

31 B18

30 CLKBA

29 CLKENBA

Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA, and CLKENBA.

The B-port outputs, include 25-Ω series resistors to reduce overshoot and undershoot.

The SN74ALVC162601 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)

packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the same

printed-circuit-board area.

The SN74ALVC162601 is characterized for operation from −40°C to 85°C.

EPIC, UBT, and Widebus are trademarks of Texas Instruments Incorporated.

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9−1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

12 3 4 5 6 7...9

中文翻译

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SN74ALVC162601 替代型号

型号	品牌	替代类型	描述	数据表
SN74ALVCH162601	TI	功能相似	18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

与SN74ALVC162601相关器件

型号	品牌	获取价格	描述	数据表
SN74ALVC162601DGG	TI	获取价格	ALVC/VCX/A SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56
SN74ALVC162601DGGR	TI	获取价格	暂无描述
SN74ALVC162601DL	TI	获取价格	18-Bit Universal Bus Transceiver With 3-State Outputs 56-SSOP -40 to 85
SN74ALVC162601DLR	TI	获取价格	18-Bit Universal Bus Transceiver With 3-State Outputs 56-SSOP -40 to 85
SN74ALVC16260DGG	TI	获取价格	ALVC/VCX/A SERIES, 12 MULTIPLEXER AND DEMUX/DECODER, PDSO56, TSSOP-56
SN74ALVC16260DGGR	ETC	获取价格	Bus Exchanger
SN74ALVC16260DL	TI	获取价格	12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74ALVC16260DLR	TI	获取价格	暂无描述
SN74ALVC16269	TI	获取价格	12-BIT TO 24-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74ALVC16269DGG	TI	获取价格	ALVC/VCX/A SERIES, 12-BIT EXCHANGER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP-56

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