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SN74ALVC10PW PDF预览

SN74ALVC10PW

更新时间: 2024-11-17 22:39:47
品牌 Logo 应用领域
德州仪器 - TI 输入元件
页数 文件大小 规格书
7页 112K
描述
TRIPLE 3-INPUT POSITIVE-NAND GATE

SN74ALVC10PW 数据手册

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SN74ALVC10  
TRIPLE 3-INPUT POSITIVE-NAND GATE  
SCES106D – JULY 1997 – REVISED OCTOBER 1998  
D, DGV, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
1A  
1B  
2A  
2B  
2C  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1C  
1Y  
3C  
3B  
3A  
3Y  
Latch-Up Performance Exceeds 250 mA  
Per JESD 17  
Package Options Include Plastic  
Small-Outline (D), Thin Very Small-Outline  
(DGV), and Thin Shrink Small-Outline (PW)  
Packages  
2Y  
GND  
8
description  
This triple 3-input positive-NAND gate is designed for 1.65-V to 3.6-V V  
operation.  
CC  
The SN74ALVC10 performs the Boolean function Y = A B C or Y = A + B + C in positive logic.  
The SN74ALVC10 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
H
L
B
H
X
L
C
H
X
X
L
L
H
H
H
X
X
X
logic symbol  
1
&
1A  
1B  
1C  
2A  
2B  
2C  
3A  
3B  
3C  
2
12  
6
1Y  
2Y  
3Y  
13  
3
4
5
9
10  
11  
8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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