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SN74ALVC00 PDF预览

SN74ALVC00

更新时间: 2024-11-17 22:05:39
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德州仪器 - TI 输入元件
页数 文件大小 规格书
7页 112K
描述
QUADRUPLE 2-INPUT POSITIVE-NAND GATE

SN74ALVC00 数据手册

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SN74ALVC00  
QUADRUPLE 2-INPUT POSITIVE-NAND GATE  
SCES115C – JULY 1997 – REVISED AUGUST 1998  
D, DGV, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
1A  
1B  
1Y  
2A  
2B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
4B  
4A  
4Y  
3B  
3A  
3Y  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Package Options Include Plastic  
Small-Outline (D), Thin Very Small-Outline  
(DGV), and Thin Shrink Small-Outline (PW)  
Packages  
2Y  
GND  
8
description  
This quadruple 2-input positive-NAND gate is designed for 1.65-V to 3.6-V V  
operation.  
CC  
The SN74ALVC00 performs the Boolean function Y = A B or Y = A + B in positive logic.  
The SN74ALVC00 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
B
H
X
L
H
L
L
H
H
X
logic symbol  
1
1A  
1B  
2A  
2B  
3A  
3B  
4A  
4B  
&
3
6
2
1Y  
2Y  
3Y  
4Y  
4
5
9
8
10  
12  
13  
11  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
logic diagram, each gate (positive logic)  
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74ALVC00 替代型号

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