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SN74ALS666DW PDF预览

SN74ALS666DW

更新时间: 2024-10-31 23:06:15
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
8页 127K
描述
8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES WITH 3-STATE OUTPUTS

SN74ALS666DW 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOIC-24针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.83Is Samacsys:N
其他特性:WITH CLEAR AND PRESET; WITH DUAL OUTPUT ENABLE; WITH READ-BACK控制类型:ENABLE LOW/HIGH
计数方向:UNIDIRECTIONAL系列:ALS
JESD-30 代码:R-PDSO-G24JESD-609代码:e4
长度:15.4 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP24,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TUBE峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):73 mA
Prop。Delay @ Nom-Sup:18 ns传播延迟(tpd):27 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Bus Driver/Transceiver最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:7.5 mm
Base Number Matches:1

SN74ALS666DW 数据手册

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SN74ALS666, SN74ALS667  
8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES  
WITH 3-STATE OUTPUTS  
SDAS227A – JUNE 1984 – REVISED JANUARY 1995  
SN74ALS666 . . . DW OR NT PACKAGE  
(TOP VIEW)  
3-State I/O-Type Read-Back Inputs  
Bus-Structured Pinout  
Choice of True or Inverting Logic  
– SN74ALS666 . . . True Outputs  
– SN74ALS667 . . . Inverted Outputs  
OERB  
OE1  
1D  
V
CC  
OE2  
1Q  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
2
3
2D  
2Q  
Preset and Clear Inputs  
Package Options Include Plastic  
Small-Outline (DW) Packages and Standard  
Plastic (NT) 300-mil DIPs  
4
3D  
3Q  
5
4D  
4Q  
6
5D  
5Q  
7
6D  
6Q  
8
7D  
7Q  
9
description  
8D  
8Q  
10  
11  
These 8-bit D-type transparent latches are  
designed specifically for storing the contents of  
the input data bus, plus reading back the stored  
data onto the input data bus. In addition, they  
provide a 3-state buffer-type output and are easily  
utilized in bus-structured applications.  
CLR  
PRE  
GND 12  
13 LE  
SN74ALS667 . . . DW OR NT PACKAGE  
(TOP VIEW)  
While the latch enable (LE) is high, the Q outputs  
oftheSN74ALS666followthedata(D)inputs. The  
Q outputs of the SN74ALS667 provide the inverse  
of the data applied to its D inputs. The Q or  
Q output of both devices is in the high-impedance  
state if either output-enable (OE1 or OE2) input is  
at a high logic level.  
OERB  
OE1  
1D  
V
CC  
OE2  
1Q  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
2
3
2D  
2Q  
4
3D  
3Q  
5
4D  
4Q  
6
5D  
5Q  
7
Read back is provided through the read-back  
control (OERB) input. When OERB is taken low,  
the data present at the output of the data latches  
passes back onto the input data bus. When OERB  
is taken high, the output of the data latches is  
isolated from the D inputs. OERB does not affect  
the internal operation of the latches; however,  
caution should be exercised to avoid a bus  
conflict.  
6D  
6Q  
8
7D  
7Q  
9
8D  
8Q  
10  
11  
CLR  
PRE  
GND 12  
13 LE  
The SN74ALS666 and SN74ALS667 are  
characterized for operation from 0°C to 70°C.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74ALS666DW 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALS666NT TI

完全替代

8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES WITH 3-STATE OUTPUTS

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