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SN74ALS642A-1N PDF预览

SN74ALS642A-1N

更新时间: 2024-11-25 12:28:35
品牌 Logo 应用领域
德州仪器 - TI 总线收发器
页数 文件大小 规格书
17页 705K
描述
Bidirectional Bus Transceivers in High-Density 20-Pin Packages

SN74ALS642A-1N 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:DIP
包装说明:DIP, DIP20,.3针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:2.09其他特性:WITH DIRECTION CONTROL
控制类型:COMMON CONTROL计数方向:BIDIRECTIONAL
系列:ALSJESD-30 代码:R-PDIP-T20
JESD-609代码:e4长度:24.33 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS TRANSCEIVER
最大I(ol):0.048 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:70 °C
最低工作温度:输出特性:OPEN-COLLECTOR
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):28 mA
Prop。Delay @ Nom-Sup:30 ns传播延迟(tpd):22 ns
认证状态:Not Qualified施密特触发器:No
座面最大高度:5.08 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
宽度:6.35 mmBase Number Matches:1

SN74ALS642A-1N 数据手册

 浏览型号SN74ALS642A-1N的Datasheet PDF文件第2页浏览型号SN74ALS642A-1N的Datasheet PDF文件第3页浏览型号SN74ALS642A-1N的Datasheet PDF文件第4页浏览型号SN74ALS642A-1N的Datasheet PDF文件第5页浏览型号SN74ALS642A-1N的Datasheet PDF文件第6页浏览型号SN74ALS642A-1N的Datasheet PDF文件第7页 
ꢋ ꢌꢍꢄꢅꢉꢎ ꢏꢀꢉ ꢍꢐꢄ ꢁꢀꢌ ꢑꢒ ꢓ ꢑꢐ  
SDAS300 − MARCH 1995  
DW OR N PACKAGE  
(TOP VIEW)  
Bidirectional Bus Transceivers in  
High-Density 20-Pin Packages  
Choice of True or Inverting Logic  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
DIR  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
V
CC  
Package Options Include Plastic  
Small-Outline (DW) Packages and  
Standard Plastic (N) 300-mil DIPs  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
DEVICE  
LOGIC  
True  
SN74ALS641A, SN74AS641  
SN74ALS642A  
Inverting  
GND  
description  
These octal bus transceivers are designed for  
asynchronous two-way communication between  
data buses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending  
upon the level at the direction-control (DIR) input. The output-enable (OE) input disables the device so that the  
buses are effectively isolated.  
The -1 versions of the SN74ALS641A and SN74ALS642A are identical to the standard versions, except that  
the recommended maximum I is increased to 48 mA in the -1 versions.  
OL  
The SN74ALS641A, SN74ALS642A, and SN74AS641 are characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
OPERATION  
SN74ALS641A  
OE  
DIR  
SN74ALS642A  
SN74AS641  
B data to A bus  
A data to B bus  
Isolation  
L
L
L
H
X
B data to A bus  
A data to B bus  
Isolation  
H
ꢍꢤ  
Copyright 1995, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

SN74ALS642A-1N 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALS642A-1NSR TI

完全替代

OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS
SN74ALS642A-1DW TI

完全替代

OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS

与SN74ALS642A-1N相关器件

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SN74ALS642A-1N3 TI

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IC,BUS TRANSCEIVER,SINGLE,8-BIT,ALS-TTL,DIP,20PIN,PLASTIC
SN74ALS642A-1NSR TI

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SN74ALS642A-1NSRG4 TI

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SN74ALS642ADW TI

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OCTAL BUS TRANSCEIVERS WITH OPEN-COLLECTOR OUTPUTS
SN74ALS642ADW3 TI

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IC,BUS TRANSCEIVER,SINGLE,8-BIT,ALS-TTL,SOP,20PIN,PLASTIC