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SN74ALS574ADW PDF预览

SN74ALS574ADW

更新时间: 2024-11-20 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
25页 1247K
描述
IC ALS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, Bus Driver/Transceiver

SN74ALS574ADW 技术参数

是否Rohs认证:不符合生命周期:Obsolete
Reach Compliance Code:not_compliant风险等级:5.42
Is Samacsys:N其他特性:BROADSIDE VERSION OF 374
系列:ALSJESD-30 代码:R-PDSO-G20
长度:12.8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):27 mA传播延迟(tpd):14 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.5 mmBase Number Matches:1

SN74ALS574ADW 数据手册

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SN54ALS574B, SN54AS574, SN54AS575  
SN74ALS574B, SN74ALS575A, SN74AS574, SN74AS575  
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS  
SDAS165B – JUNE 1982 – REVISED JULY 1995  
SN54ALS574B, SN54AS574 . . . J OR W PACKAGE  
SN74ALS574B, SN74AS574 . . . DW OR N PACKAGE  
(TOP VIEW)  
3-State Buffer-Type Noninverting Outputs  
Drive Bus Lines Directly  
Bus-Structured Pinout  
Buffered Control Inputs  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19 1Q  
18 2Q  
17  
16  
15  
14  
13  
12  
11  
SN74ALS575A and AS575 Have  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
CLK  
Synchronous Clear  
Package Options Include Plastic  
Small-Outline (DW) Packages, Ceramic  
Chip Carriers (FK), Standard Plastic (N, NT)  
and Ceramic (J, JT) 300-mil DIPs, and  
Ceramic Flat (W) Packages  
GND  
SN54ALS574B, SN54AS574 . . . FK PACKAGE  
(TOP VIEW)  
description  
These octal D-type edge-triggered flip-flops  
feature 3-state outputs designed specifically for  
bus driving. They are particularly suitable for  
implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers.  
3
9
2
1 20 19  
18 2Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
15  
14  
3Q  
4Q  
5Q  
6Q  
The eight flip-flops enter data on the low-to-high  
transition of the clock (CLK) input. The  
SN74ALS575A, SN54AS575, and SN74AS575  
may be synchronously cleared by taking the clear  
(CLR) input low.  
10 11 1213  
SN54AS575 . . . JT OR W PACKAGE  
SN74ALS575A, SN74AS575 . . . DW OR NT PACKAGE  
(TOP VIEW)  
The output-enable (OE) input does not affect  
internal operations of the flip-flops. Old data can  
be retained or new data can be entered while the  
outputs are in the high-impedance state.  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
CLR  
OE  
1D  
V
CC  
NC  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
CLK  
NC  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
The  
SN54ALS574B,  
SN54AS574,  
and  
SN54AS575 are characterized for operation over  
the full military temperature range of 55°C to  
125°C. The SN74ALS574B, SN74ALS575A,  
SN74AS574, and SN74AS575 are characterized  
for operation from 0°C to 70°C.  
9
10  
11  
12  
NC  
GND  
SN54AS575 . . . FK PACKAGE  
(TOP VIEW)  
4
3
2
1 28 27 26  
5
6
7
8
9
25  
24  
23  
22  
21  
20  
19  
2D  
3D  
4D  
NC  
5D  
6D  
7D  
2Q  
3Q  
4Q  
NC  
5Q  
6Q  
7Q  
10  
11  
1213  
18  
14 15 16 17  
NC – No internal connection  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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