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SN74ALS534AN3

更新时间： 2024-11-04 05:17:47
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
14页 452K
描述
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

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SN74ALS534AN3 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP20,.3针数：20
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.51系列：ALS
JESD-30 代码：R-PDIP-T20长度：25.4 mm
逻辑集成电路类型：BUS DRIVER最大频率@ Nom-Sup：35000000 Hz
最大I（ol）：0.024 A位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP20,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
最大电源电流（ICC）：31 mA传播延迟（tpd）：16 ns
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：TTL
温度等级：COMMERCIAL端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：7.62 mmBase Number Matches：1

SN74ALS534AN3 数据手册

 浏览型号SN74ALS534AN3的Datasheet PDF文件第2页浏览型号SN74ALS534AN3的Datasheet PDF文件第3页浏览型号SN74ALS534AN3的Datasheet PDF文件第4页浏览型号SN74ALS534AN3的Datasheet PDF文件第5页浏览型号SN74ALS534AN3的Datasheet PDF文件第6页浏览型号SN74ALS534AN3的Datasheet PDF文件第7页 
SN54ALS534A, SN74ALS534A, SN74AS534  
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SDAS168B – APRIL 1982 – REVISED JULY 1996  
SN54ALS534A . . . J PACKAGE  
SN74ALS534A, SN74AS534 . . . DW OR N PACKAGE  
(TOP VIEW)  
3-State Bus Driving Inverting Outputs  
Buffered Control Inputs  
Package Options Include Plastic  
Small-Outline (DW), Ceramic Chip Carriers  
(FK), and Standard Plastic (N) and Ceramic  
(J) 300-mil DIPs  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
8Q  
8D  
7D  
7Q  
6Q  
6D  
description  
These octal D-type edge-triggered flip-flops  
feature 3-state outputs designed specifically for  
driving highly capacitive or relatively low-  
impedance loads. They are particularly suitable  
for implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers.  
13 5D  
12 5Q  
11  
GND  
CLK  
SN54ALS534A . . . FK PACKAGE  
(TOP VIEW)  
On the positive transition of the clock (CLK) input,  
the Q outputs are set to the complement of the  
logic states set up at the data (D) inputs. The  
’ALS534A and SN74AS534 have inverted out-  
puts, but otherwise are functionally equivalent to  
the ’ALS374A and SN74AS374.  
3
2
1
20 19  
18  
8D  
7D  
7Q  
6Q  
6D  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
17  
16  
15  
14  
A buffered output-enable (OE) input places the  
eight outputs in either a normal logic state (high or  
low logic levels) or a high-impedance state. In the  
high-impedance state, the outputs neither load  
nor drive the bus lines significantly. The  
high-impedance state and increased drive  
provide the capability to drive bus lines without  
interface or pullup components.  
9 10 11 12 13  
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are off.  
The SN54ALS534A is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74ALS534A and SN74AS534 are characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
OE  
L
CLK  
D
H
L
↑
↑
L
L
H
L
H or L  
X
X
X
Q
0
H
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...14

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