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SN74ALS29845FNR PDF预览

SN74ALS29845FNR

更新时间: 2024-09-09 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
7页 75K
描述
ALS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PQCC28, PLASTIC, QCC-28

SN74ALS29845FNR 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCJ,针数:28
Reach Compliance Code:unknown风险等级:5.82
系列:ALSJESD-30 代码:R-PQCC-J28
长度:11.5062 mm逻辑集成电路类型:BUS DRIVER
位数:8功能数量:1
端口数量:2端子数量:28
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
传播延迟(tpd):14 ns认证状态:Not Qualified
座面最大高度:4.57 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
宽度:11.5062 mmBase Number Matches:1

SN74ALS29845FNR 数据手册

 浏览型号SN74ALS29845FNR的Datasheet PDF文件第2页浏览型号SN74ALS29845FNR的Datasheet PDF文件第3页浏览型号SN74ALS29845FNR的Datasheet PDF文件第4页浏览型号SN74ALS29845FNR的Datasheet PDF文件第5页浏览型号SN74ALS29845FNR的Datasheet PDF文件第6页浏览型号SN74ALS29845FNR的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢅ ꢀ ꢆꢇ ꢈ ꢃ ꢉ ꢊ ꢀꢁꢂ ꢃ ꢄ ꢅꢀ ꢆꢇ ꢈꢃ ꢋ  
ꢗꢐ  
SDAS150 − D3118 — JUNE 1988  
3-State Buffer-Type Outputs Drive Bus  
SN74ALS29845 . . . DW or NT Package  
(Top View)  
Lines Directly  
Bus-Structured Pinout  
1
24  
23  
22  
21  
20  
19  
18  
OC1  
OC2  
1D  
V
CC  
Provides Extra Bus Driving Latches  
2
OC3  
1Q  
2Q  
3Q  
4Q  
5Q  
3
Necessary For Wider Address/Data Paths  
or Buses With Parity  
4
2D  
5
3D  
Buffered Control Inputs to Reduce DC  
6
4D  
7
5D  
Loading  
6D  
8
17 6Q  
16 7Q  
15 8Q  
14 PRE  
Power-Up High-Impedance State  
7D  
9
8D  
10  
11  
12  
Package Options Include Plastic “Small  
Outline” Packages, Plastic Chip Carriers,  
and Standard Plastic 300-mil DIPs  
CLR  
GND  
13  
C
Dependable Texas Instruments Quality and  
SN74ALS29845 . . . FN Package  
(Top View)  
Reliability  
description  
4
3
2
1
28 27 26  
25  
2D  
3D  
4D  
NC  
5D  
2Q  
3Q  
4Q  
NC  
5Q  
6Q  
7Q  
5
6
7
8
9
These 8-bit latches feature three-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. They are  
particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
24  
23  
22  
21  
20  
19  
6D 10  
11  
12 13 14 15 16 17 18  
7D  
The eight latches are transparent D-type. The  
ALS29845 has noninverting data (D) inputs. The  
ALS29846 has inverting D inputs. Since CLR and  
PRE are independent of the clock, taking the CLR  
input low will cause the eight Q outputs to go low.  
Taking the PRE input low will cause the eight Q  
outputs to go high. When both PRE and CLR are  
taken low, the outputs will follow the preset  
condition.  
SN74ALS29846 . . . DW or NT Package  
(Top View)  
1
24  
23  
22  
21  
20  
19  
OC1  
OC2  
1D  
V
CC  
2
OC3  
3
1Q  
4
2D  
2Q  
5
3D  
3Q  
6
4D  
4Q  
5D  
7
18 5Q  
17 6Q  
16 7Q  
15 8Q  
14 PRE  
The buffered output control inputs (OC1, OC2,  
and OC3) can be used to place the eight outputs  
in either a normal logic state (high or low levels) or  
a high-impedance state. The outputs are also in  
the high-impedance state during power-up and  
power-down conditions. The outputs remain in the  
high-impedance state while the device is  
powered-down. In the high-impedance state, the  
outputs neither load nor drive the bus lines  
significantly. The high-impedance state and  
increased drive provide the capability to drive the  
bus lines in a bus-organized system without need  
6D  
8
7D  
9
8D  
10  
11  
12  
CLR  
GND  
13  
C
SN74ALS29846 . . . FN Package  
(Top View)  
4
3
2
1
28 27 26  
25  
2D  
3D  
4D  
NC  
5D  
6D  
7D  
2Q  
3Q  
4Q  
NC  
5
6
24  
23  
22  
7
8
9
21 5Q  
20 6Q  
10  
11  
19  
7Q  
12 13 14 15 16 17 18  
NC — No internal connection  
ꢗꢒ ꢛ ꢕꢐ ꢔ ꢏꢎ ꢛ ꢁ ꢕ ꢄꢏꢄ ꢜꢝ ꢞ ꢟꢠꢡ ꢢꢣ ꢜꢟꢝ ꢜꢤ ꢥꢦ ꢠ ꢠ ꢧꢝꢣ ꢢꢤ ꢟꢞ  
Copyright 1988, Texas Instruments Incorporated  
ꢝꢧ ꢥ ꢧ ꢤ ꢤ ꢢ ꢠꢜ ꢪꢰ ꢜꢝ ꢥ ꢪꢦ ꢫꢧ ꢣ ꢧ ꢤ ꢣꢜ ꢝꢱ ꢟꢞ ꢢꢪ ꢪ ꢨꢢ ꢠ ꢢꢡ ꢧꢣꢧ ꢠ ꢤꢬ  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
1

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