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SN74ALS29833NT

更新时间： 2024-09-08 22:50:27
品牌 Logo 应用领域
德州仪器 - TI 总线收发器
页数 文件大小 规格书
6页 104K
描述
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER

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中文翻译

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SN74ALS29833NT 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP24,.3针数：24
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.86其他特性：INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION; PARITY GENERATION A TO B; ERROR DETECTION B TO A
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：ALSJESD-30 代码：R-PDIP-T24
长度：31.64 mm负载电容（CL）：300 pF
逻辑集成电路类型：BUS TRANSCEIVER位数：8
功能数量：1端口数量：2
端子数量：24最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP24,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED最大电源电流（ICC）：100 mA
传播延迟（tpd）：15 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：TTL温度等级：COMMERCIAL
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：7.62 mm
Base Number Matches：1

SN74ALS29833NT 数据手册

 浏览型号SN74ALS29833NT的Datasheet PDF文件第2页浏览型号SN74ALS29833NT的Datasheet PDF文件第3页浏览型号SN74ALS29833NT的Datasheet PDF文件第4页浏览型号SN74ALS29833NT的Datasheet PDF文件第5页浏览型号SN74ALS29833NT的Datasheet PDF文件第6页 
SN74ALS29833  
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER  
SDAS119D – FEBRUARY 1987 – REVISED JANUARY 1995  
DW OR NT PACKAGE  
(TOP VIEW)  
• Functionally Similar to AMD’s AM29833  
• High-Speed Bus Transceiver With Parity  
Generator/Checker  
OEA  
A1  
V
CC  
B1  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
• Parity-Error Flag With Open-Collector  
2
Outputs  
A2  
B2  
3
• Register for Storing the Parity-Error Flag  
• Package Options Include Plastic  
Small-Outline (DW) Packages and Standard  
Plastic (NT) 300-mil DIPs  
A3  
B3  
4
A4  
B4  
5
A5  
B5  
6
A6  
B6  
7
A7  
B7  
8
description  
A8  
B8  
9
ERR  
CLR  
PARITY  
OEB  
10  
11  
The SN74ALS29833 is an 8-bit to 9-bit parity  
transceiver designed for two-way communication  
between data buses. When data is transmitted  
from the A bus to the B bus, a parity bit is  
GND 12  
13 CLK  
generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the parity-error  
(ERR) output indicates whether or not an error in the B data has occurred. The output-enable (OEA, OEB) inputs  
can be used to disable the device so that the buses are effectively isolated.  
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports  
with an open-collector ERR flag. ERR is clocked into the register on the rising edge of the clock (CLK) input.  
The error-flag register is cleared with a low pulse on the clear (CLR) input. When both OEA and OEB are low,  
data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error  
condition that gives the designer more system diagnostic capability.  
The SN74ALS29833 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
CLK  
OUTPUT AND I/O  
†
Bi  
∑ of Ls  
FUNCTION  
Ai  
∑ of Hs  
‡
A
B
PARITY  
OEB  
OEA  
CLR  
ERR  
Odd  
L
L
H
X
X
NA  
NA  
A
NA  
A data to B bus and generate parity  
Even  
H
Odd  
Even  
X
H
L
H
X
L
H
NA  
B
X
NA  
NA  
NA  
NA  
B data to A bus and check parity  
Clear error-flag register  
↑
X
L
H
L
X
No↑  
No↑  
↑
X
X
H
NC  
H
X
§
H
L
H
L
X
Z
Z
A
Z
Isolation  
H
H
Odd  
Even  
Odd  
Even  
H
↑
L
H
L
A data to B bus and generate inverted  
parity  
X
X
NA  
NA  
NA  
NA = not applicable, NC = no change, X = don’t care  
†
‡
§
Summation of high-level inputs includes PARITY along with Bi inputs.  
Output states shown assume ERR was previously high.  
In this mode, ERR, when clocked, shows inverted parity of the A bus.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
123456

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