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SN74ALS29833

更新时间： 2024-11-18 22:50:27
品牌 Logo 应用领域
德州仪器 - TI 总线收发器
页数 文件大小 规格书
6页 104K
描述
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER

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SN74ALS29833 数据手册

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SN74ALS29833  
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER  
SDAS119D – FEBRUARY 1987 – REVISED JANUARY 1995  
DW OR NT PACKAGE  
(TOP VIEW)  
• Functionally Similar to AMD’s AM29833  
• High-Speed Bus Transceiver With Parity  
Generator/Checker  
OEA  
A1  
V
CC  
B1  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
• Parity-Error Flag With Open-Collector  
2
Outputs  
A2  
B2  
3
• Register for Storing the Parity-Error Flag  
• Package Options Include Plastic  
Small-Outline (DW) Packages and Standard  
Plastic (NT) 300-mil DIPs  
A3  
B3  
4
A4  
B4  
5
A5  
B5  
6
A6  
B6  
7
A7  
B7  
8
description  
A8  
B8  
9
ERR  
CLR  
PARITY  
OEB  
10  
11  
The SN74ALS29833 is an 8-bit to 9-bit parity  
transceiver designed for two-way communication  
between data buses. When data is transmitted  
from the A bus to the B bus, a parity bit is  
GND 12  
13 CLK  
generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the parity-error  
(ERR) output indicates whether or not an error in the B data has occurred. The output-enable (OEA, OEB) inputs  
can be used to disable the device so that the buses are effectively isolated.  
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports  
with an open-collector ERR flag. ERR is clocked into the register on the rising edge of the clock (CLK) input.  
The error-flag register is cleared with a low pulse on the clear (CLR) input. When both OEA and OEB are low,  
data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error  
condition that gives the designer more system diagnostic capability.  
The SN74ALS29833 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
CLK  
OUTPUT AND I/O  
†
Bi  
∑ of Ls  
FUNCTION  
Ai  
∑ of Hs  
‡
A
B
PARITY  
OEB  
OEA  
CLR  
ERR  
Odd  
L
L
H
X
X
NA  
NA  
A
NA  
A data to B bus and generate parity  
Even  
H
Odd  
Even  
X
H
L
H
X
L
H
NA  
B
X
NA  
NA  
NA  
NA  
B data to A bus and check parity  
Clear error-flag register  
↑
X
L
H
L
X
No↑  
No↑  
↑
X
X
H
NC  
H
X
§
H
L
H
L
X
Z
Z
A
Z
Isolation  
H
H
Odd  
Even  
Odd  
Even  
H
↑
L
H
L
A data to B bus and generate inverted  
parity  
X
X
NA  
NA  
NA  
NA = not applicable, NC = no change, X = don’t care  
†
‡
§
Summation of high-level inputs includes PARITY along with Bi inputs.  
Output states shown assume ERR was previously high.  
In this mode, ERR, when clocked, shows inverted parity of the A bus.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
123456

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