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SN74ALS29823FN

更新时间： 2024-11-19 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
7页 112K
描述
ALS SERIES, 9-BIT DRIVER, TRUE OUTPUT, PQCC28

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SN74ALS29823FN 技术参数

是否Rohs认证：不符合生命周期：Obsolete
Reach Compliance Code：not_compliant风险等级：5.84
Is Samacsys：N其他特性：WITH CLEAR AND CLOCK ENABLE; POWER OFF DISABLE OUTPUTS TO PERMIT LIVE INSERTION
系列：ALSJESD-30 代码：S-PQCC-J28
长度：11.5062 mm逻辑集成电路类型：BUS DRIVER
位数：9功能数量：1
端口数量：2端子数量：28
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC28,.5SQ封装形状：SQUARE
封装形式：CHIP CARRIER峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V认证状态：Not Qualified
座面最大高度：4.57 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：TTL温度等级：COMMERCIAL
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：11.5062 mm
Base Number Matches：1

SN74ALS29823FN 数据手册

 浏览型号SN74ALS29823FN的Datasheet PDF文件第2页浏览型号SN74ALS29823FN的Datasheet PDF文件第3页浏览型号SN74ALS29823FN的Datasheet PDF文件第4页浏览型号SN74ALS29823FN的Datasheet PDF文件第5页浏览型号SN74ALS29823FN的Datasheet PDF文件第6页浏览型号SN74ALS29823FN的Datasheet PDF文件第7页 
SN54ALS29823, SN74ALS29823  
9-BIT BUS-INTERFACE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SDAS146B – JANUARY 1986 – REVISED JANUARY 1995  
SN54ALS29823 . . . JT PACKAGE  
SN74ALS29823 . . . DW OR NT PACKAGE  
(TOP VIEW)  
• Functionally Equivalent to AMD’s AM29823  
• Provide Extra Data Width Necessary for  
Wider Address/Data Paths or Buses With  
Parity  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
24  
• Outputs Have Undershoot-Protection  
23 1Q  
22 2Q  
21 3Q  
20 4Q  
19 5Q  
18 6Q  
17 7Q  
16 8Q  
15 9Q  
14 CLKEN  
13 CLK  
Circuitry  
• Power-Up High-Impedance State  
• Buffered Control Inputs Reduce dc Loading  
Effects  
• Package Options Include Plastic  
Small-Outline (DW) Packages and Standard  
Plastic (NT) and Ceramic (JT) 300-mil DIPs  
9D 10  
CLR 11  
GND 12  
description  
These 9-bit flip-flops feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O  
ports, bidirectional bus drivers, parity bus interfacing, and working registers.  
With the clock-enable (CLKEN) input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high  
transitions of the clock (CLK) input. Taking CLKEN high disables the clock buffer, latching the outputs. The  
′ALS29823 have noninverting data (D) inputs. Taking the clear (CLR) input low causes the nine Q outputs to  
go low independently of the clock.  
Abufferedoutput-enable(OE)inputplacesthenineoutputsineitheranormallogicstate(highorlowlogiclevels)  
or a high-impedance state. The outputs also are in the high-impedance state during power-up and power-down  
conditions. The outputs remain in the high-impedance state while the device is powered down. In the  
high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state  
and increased drive provide the capability to drive bus lines without interface or pullup components.  
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
The SN54ALS29823 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74ALS29823 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
OE  
L
CLR CLKEN CLK  
D
X
H
L
L
H
H
H
X
X
L
X
↑
L
H
L
L
L
L
↑
L
H
X
X
X
X
X
Q
0
H
Z
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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