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SN74ALS29821NT3 PDF预览

SN74ALS29821NT3

更新时间: 2024-11-19 21:04:15
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
11页 247K
描述
ALS SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDIP24

SN74ALS29821NT3 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP24,.3Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.18
其他特性:POWER OFF DISABLE OUTPUTS TO PERMIT LIVE INSERTION系列:ALS
JESD-30 代码:R-PDIP-T24长度:31.64 mm
逻辑集成电路类型:BUS DRIVER位数:10
功能数量:1端口数量:2
端子数量:24最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP24,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:5.08 mm子类别:FF/Latches
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
Base Number Matches:1

SN74ALS29821NT3 数据手册

 浏览型号SN74ALS29821NT3的Datasheet PDF文件第2页浏览型号SN74ALS29821NT3的Datasheet PDF文件第3页浏览型号SN74ALS29821NT3的Datasheet PDF文件第4页浏览型号SN74ALS29821NT3的Datasheet PDF文件第5页浏览型号SN74ALS29821NT3的Datasheet PDF文件第6页浏览型号SN74ALS29821NT3的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢀ ꢆꢇ ꢈ ꢆ ꢉ ꢊꢋ ꢀꢁꢌ ꢃ ꢄ ꢅꢀ ꢆꢇ ꢈꢆ ꢉ  
ꢉ ꢍ ꢎꢏꢐ ꢑꢋ ꢏꢒꢀꢎꢐ ꢁꢑ ꢓꢔꢕꢄꢖꢓ ꢋꢕ ꢅꢐ ꢗ ꢎꢕ ꢅꢘ ꢗ ꢀ  
ꢙ ꢐꢑ ꢚꢋ ꢛ ꢎꢀꢑꢄꢑ ꢓꢋ ꢘ ꢒꢑ ꢗꢒ ꢑꢀ  
SDAS145B − JANUARY 1986 − REVISED JANUARY 1995  
SN54ALS29821 . . . JT PACKAGE  
SN74ALS29821 . . . DW OR NT PACKAGE  
(TOP VIEW)  
Functionally Equivalent to AMD’s AM29821  
Provide Extra Data Width Necessary for  
Wider Address/Data Paths or Buses With  
Parity  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
24  
Outputs Have Undershoot-Protection  
23 1Q  
22 2Q  
21 3Q  
20 4Q  
19 5Q  
18 6Q  
17 7Q  
16 8Q  
15 9Q  
14 10Q  
13 CLK  
Circuitry  
Power-Up High-Impedance State  
Buffered Control Inputs Reduce  
dc Loading Effects  
Package Options Include Plastic  
Small-Outline (DW) Packages and Standard  
Plastic (NT) and Ceramic (JT) 300-mil DIPs  
9D 10  
10D 11  
GND 12  
description  
These 10-bit edge-triggered D-type flip-flops  
feature 3-state outputs designed specifically for  
driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for  
implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.  
On the positive transition of the clock (CLK) input, the Q outputs are true to the data (D) input.  
A buffered output-enable (OE) input can place the ten outputs in either a normal logic state (high or low logic  
levels) or a high-impedance state. The outputs also are in the high-impedance state during power-up and  
power-down conditions. The outputs remain in the high-impedance state while the device is powered down. In  
the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance  
state and increased drive provide the capability to drive bus lines without interface or pullup components.  
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
The SN54ALS29821 is characterized for operation over the full military temperature range of 55°C to 125°C.  
The SN74ALS29821 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
OE  
L
CLK  
D
H
L
H
L
L
L
L
X
X
Q
0
H
X
Z
ꢑꢨ  
Copyright 1995, Texas Instruments Incorporated  
ꢤ ꢨ ꢥ ꢤꢝ ꢞꢲ ꢠꢟ ꢣ ꢫꢫ ꢩꢣ ꢡ ꢣ ꢢ ꢨ ꢤ ꢨ ꢡ ꢥ ꢭ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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