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SN74ALS21ANSRG4 PDF预览

SN74ALS21ANSRG4

更新时间: 2024-09-26 15:52:07
品牌 Logo 应用领域
德州仪器 - TI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
17页 844K
描述
Dual 4-Input Positive-AND Gates 14-SO 0 to 70

SN74ALS21ANSRG4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP14,.3针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.74系列:ALS
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:10.2 mm逻辑集成电路类型:AND GATE
最大I(ol):0.008 A湿度敏感等级:1
功能数量:2输入次数:4
端子数量:14最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):2.3 mA
Prop。Delay @ Nom-Sup:15 ns传播延迟(tpd):15 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:2 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.3 mm
Base Number Matches:1

SN74ALS21ANSRG4 数据手册

 浏览型号SN74ALS21ANSRG4的Datasheet PDF文件第2页浏览型号SN74ALS21ANSRG4的Datasheet PDF文件第3页浏览型号SN74ALS21ANSRG4的Datasheet PDF文件第4页浏览型号SN74ALS21ANSRG4的Datasheet PDF文件第5页浏览型号SN74ALS21ANSRG4的Datasheet PDF文件第6页浏览型号SN74ALS21ANSRG4的Datasheet PDF文件第7页 
ꢋꢌꢄ ꢅꢉꢃ ꢍꢎ ꢁꢏꢌ ꢐꢉ ꢏꢑ ꢀꢎ ꢐ ꢎꢒꢓ ꢍꢄꢁꢋ ꢉꢔ ꢄꢐꢓ  
SDAS085B − APRIL 1982 − REVISED DECEMBER 1994  
SN54ALS21A, SN54AS21 . . . J PACKAGE  
SN74ALS21A, SN74AS21 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
1A  
1B  
NC  
1C  
1D  
1Y  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
2D  
2C  
NC  
2B  
2A  
2Y  
description  
These devices contain two independent 4-input  
positive-AND gates. They perform the Boolean  
functions Y = A B C D or Y = A + B + C + D  
in positive logic.  
GND  
8
The SN54ALS21A and SN54AS21 are  
characterized for operation over the full military  
temperature range of 55°C to 125°C. The  
SN74ALS21A and SN74AS21 are characterized  
for operation from 0°C to 70°C.  
SN54ALS21A, SN54AS21 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
FUNCTION TABLE  
(each gate)  
NC  
NC  
1C  
NC  
1D  
4
5
6
7
8
2C  
NC  
NC  
NC  
2B  
17  
16  
15  
14  
INPUTS  
OUTPUT  
Y
A
H
L
B
C
H
X
X
L
D
H
X
X
X
L
H
X
L
H
L
L
L
L
9 10 11 12 13  
X
X
X
X
X
X
NC − No internal connection  
logic symbol  
logic diagram (positive logic)  
1
1
&
1A  
1A  
2
2
1B  
1B  
4
6
6
1Y  
4
5
1Y  
2Y  
1C  
1D  
1C  
5
1D  
9
2A  
9
2A  
10  
2B  
8
10  
12  
2B  
2C  
8
12  
2Y  
2C  
13  
2D  
13  
2D  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
ꢐꢢ  
Copyright 1994, Texas Instruments Incorporated  
ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ  
ꢟꢗ  
ꢠꢢ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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