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SN74ALS12AJ PDF预览

SN74ALS12AJ

更新时间: 2024-11-04 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 输出元件输入元件
页数 文件大小 规格书
3页 59K
描述
IC,LOGIC GATE,3 3-INPUT NAND,ALS-TTL,DIP,14PIN,CERAMIC

SN74ALS12AJ 技术参数

是否Rohs认证:不符合生命周期:Obsolete
Reach Compliance Code:not_compliant风险等级:5.92
Is Samacsys:NJESD-30 代码:R-XDIP-T14
逻辑集成电路类型:NAND GATE端子数量:14
最高工作温度:70 °C最低工作温度:
输出特性:OPEN-COLLECTOR封装主体材料:CERAMIC
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
认证状态:Not Qualified施密特触发器:NO
子类别:Gates表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

SN74ALS12AJ 数据手册

 浏览型号SN74ALS12AJ的Datasheet PDF文件第2页浏览型号SN74ALS12AJ的Datasheet PDF文件第3页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢀ ꢆꢇ ꢄ ꢈꢉ ꢀꢁꢊ ꢃꢄ ꢅꢀ ꢆ ꢇꢄ  
ꢋ ꢌꢍꢎ ꢅꢏ ꢉꢐ ꢑꢍ ꢁꢎꢒꢋ ꢉ ꢎꢓ ꢀꢍꢋ ꢍ ꢔꢏꢑꢁ ꢄꢁꢕ ꢉꢖ ꢄꢋꢏ ꢀ  
ꢗ ꢍꢋ ꢘꢉ ꢓꢎ ꢏꢁꢑꢙꢓ ꢅ ꢅ ꢏꢙꢋꢓ ꢌꢉꢓ ꢒꢋ ꢎꢒ ꢋꢀ  
SDAS008A − MARCH 1984 − REVISED MAY 1986  
Package Options Include Plastic Small  
Outline Packages, Ceramic Chip Carriers,  
and Standard Plastic and Ceramic 300-mil  
DIPs  
SN54ALS12A . . . J PACKAGE  
SN74ALS12A . . . D OR N PACKAGE  
(TOP VIEW)  
V
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1A  
1B  
2A  
2B  
2C  
CC  
Dependable Texas Instruments Quality and  
1C  
1Y  
3C  
3B  
3A  
3Y  
Reliability  
description  
These devices contain three independent 3-input  
NAND gates with open-collector outputs. These  
gates perform the Boolean functions Y = ABC or  
Y = A+B+C in positive logic. The open-collector  
outputs require pullup resistors to perform  
correctly. They may be connected to other  
open-collector outputs to implement active-low  
wired-OR or active-high wired-AND functions.  
Open-collector devices are often used to generate  
2Y  
GND  
8
SN54ALS12A . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
higher V  
levels.  
OH  
1Y  
NC  
3C  
NC  
3B  
2A  
NC  
2B  
4
5
6
7
8
17  
16  
15  
14  
The SN54ALS12A is characterized for operation  
over the full military temperature range of 55°C  
to 125°C. The SN74ALS12A is characterized for  
operation from 0°C to 70°C.  
NC  
2C  
9 10 11 12 13  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
NCNo internal connection  
A
H
L
B
H
X
L
C
H
X
X
L
Y
L
H
H
H
logic diagram (positive logic)  
X
X
X
1A  
1B  
1C  
1Y  
logic symbol  
1
2A  
2B  
2C  
&
1A  
1B  
1C  
2A  
2B  
2C  
3A  
2Y  
3Y  
2
12  
6
1Y  
13  
3
3A  
3B  
3C  
4
2Y  
3Y  
5
9
8
10  
11  
3B  
3C  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for D, J, and N packages.  
ꢎꢌ ꢓ ꢕꢒ ꢙ ꢋꢍ ꢓꢁ ꢕ ꢄꢋꢄ ꢛꢜ ꢝ ꢞꢟ ꢠꢡ ꢢꢛꢞ ꢜ ꢛꢣ ꢤꢥ ꢟ ꢟ ꢦꢜꢢ ꢡꢣ ꢞꢝ ꢧꢥꢨ ꢩꢛꢤ ꢡꢢ ꢛꢞꢜ ꢪꢡ ꢢꢦ ꢫ  
ꢎꢟ ꢞ ꢪꢥꢤ ꢢ ꢣ ꢤ ꢞꢜ ꢝꢞ ꢟ ꢠ ꢢ ꢞ ꢣ ꢧꢦ ꢤ ꢛꢝ ꢛꢤꢡ ꢢꢛ ꢞꢜꢣ ꢧꢦ ꢟ ꢢꢬ ꢦ ꢢꢦ ꢟ ꢠꢣ ꢞꢝ ꢋꢦꢭ ꢡꢣ ꢍꢜꢣ ꢢꢟ ꢥꢠ ꢦꢜꢢ ꢣ  
ꢣ ꢢ ꢡ ꢜꢪ ꢡ ꢟꢪ ꢮ ꢡ ꢟꢟ ꢡ ꢜ ꢢꢯꢫ ꢎꢟ ꢞ ꢪꢥꢤ ꢢꢛꢞꢜ ꢧꢟ ꢞꢤ ꢦꢣ ꢣꢛ ꢜꢰ ꢪꢞꢦ ꢣ ꢜꢞꢢ ꢜꢦ ꢤꢦ ꢣꢣ ꢡꢟ ꢛꢩ ꢯ ꢛꢜꢤ ꢩꢥꢪ ꢦ  
ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ  
Copyright 1986, Texas Instruments Incorporated  
5BASIC  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  

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