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SN74ALS1240N-10 PDF预览

SN74ALS1240N-10

更新时间: 2024-09-23 15:52:07
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
5页 86K
描述
ALS SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDIP20

SN74ALS1240N-10 技术参数

生命周期:Obsolete包装说明:DIP,
Reach Compliance Code:unknown风险等级:5.83
系列:ALSJESD-30 代码:R-PDIP-T20
长度:24.325 mm逻辑集成电路类型:BUS DRIVER
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
认证状态:Not Qualified座面最大高度:5.08 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL宽度:7.62 mm
Base Number Matches:1

SN74ALS1240N-10 数据手册

 浏览型号SN74ALS1240N-10的Datasheet PDF文件第2页浏览型号SN74ALS1240N-10的Datasheet PDF文件第3页浏览型号SN74ALS1240N-10的Datasheet PDF文件第4页浏览型号SN74ALS1240N-10的Datasheet PDF文件第5页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢀꢆ ꢇꢃ ꢈ  
ꢉ ꢊꢋꢄꢅꢌꢍ ꢎꢏ ꢏꢐ ꢑꢌꢄꢁꢒ ꢌꢅ ꢓꢁꢐ ꢌ ꢒꢑ ꢓ ꢔꢐ ꢑ  
ꢕ ꢓꢋ ꢖꢌ ꢗ ꢘꢀꢋꢄꢋ ꢐꢌ ꢉꢎ ꢋꢙ ꢎꢋ ꢀ  
SDAS054B − DECEMBER 1982 − REVISED JANUARY 1995  
DW OR N PACKAGE  
(TOP VIEW)  
Low-Power Version of SN74ALS240A  
3-State Outputs Drive Bus Lines or Buffer  
Memory Address Registers  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
pnp Inputs Reduce dc Loading  
2OE  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
Package Options Include Plastic  
Small-Outline (DW) Packages and Standard  
Plastic (N) 300-mil DIPs  
description  
13 2A2  
12 1Y4  
This octal buffer and line driver is designed  
specifically to improve both the performance and  
density of 3-state memory address drivers, clock  
drivers, and bus-oriented receivers and  
11  
2A1  
transmitters. The designer has a choice of selected combinations of inverting and noninverting outputs,  
symmetrical active-low output-enable (OE) inputs, and complementary OE and OE inputs. This device features  
high fan-out and improved fan-in.  
The SN74ALS1240 is characterized for operation from 0°C to 70°C.  
logic symbol  
logic diagram (positive logic)  
1
1OE  
1
EN  
1OE  
18  
16  
2
4
6
8
18  
16  
14  
12  
2
1Y1  
1Y2  
1Y3  
1Y4  
1A1  
1A1  
1A2  
1A3  
1A4  
1Y1  
1Y2  
1Y3  
1Y4  
4
1A2  
14  
12  
6
1A3  
19  
EN  
2OE  
8
1A4  
11  
13  
15  
17  
9
7
5
3
2A1  
2A2  
2A3  
2A4  
2Y1  
2Y2  
2Y3  
2Y4  
19  
2OE  
9
7
11  
2Y1  
2Y2  
2A1  
This symbol is in accordance with ANSI/IEEE Std 91-1984  
and IEC Publication 617-12.  
13  
2A2  
5
3
15  
2Y3  
2Y4  
2A3  
17  
2A4  
ꢋꢥ  
Copyright 1995, Texas Instruments Incorporated  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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