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SN74ALS10AFN PDF预览

SN74ALS10AFN

更新时间: 2024-11-20 13:00:03
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
16页 665K
描述
IC,LOGIC GATE,3 3-INPUT NAND,ALS-TTL,LDCC,20PIN,PLASTIC

SN74ALS10AFN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:QCCJ, LDCC20,.4SQReach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.86
JESD-30 代码:S-PQCC-J20逻辑集成电路类型:NAND GATE
端子数量:20最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC20,.4SQ
封装形状:SQUARE封装形式:CHIP CARRIER
电源:5 VProp。Delay @ Nom-Sup:11 ns
认证状态:Not Qualified施密特触发器:NO
子类别:Gates标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
Base Number Matches:1

SN74ALS10AFN 数据手册

 浏览型号SN74ALS10AFN的Datasheet PDF文件第2页浏览型号SN74ALS10AFN的Datasheet PDF文件第3页浏览型号SN74ALS10AFN的Datasheet PDF文件第4页浏览型号SN74ALS10AFN的Datasheet PDF文件第5页浏览型号SN74ALS10AFN的Datasheet PDF文件第6页浏览型号SN74ALS10AFN的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢀ ꢆꢇ ꢄ ꢈꢉ ꢀꢁꢂ ꢃ ꢄꢀꢆ ꢇ ꢈ ꢉꢀꢁꢊ ꢃ ꢄꢅ ꢀꢆ ꢇ ꢄꢈ ꢉꢀ ꢁꢊ ꢃꢄꢀ ꢆꢇ  
ꢋ ꢌꢄꢍꢎ ꢌꢏꢅ ꢐꢉ ꢇꢑꢒ ꢁꢏꢌ ꢓ ꢉꢏꢔ ꢀ ꢒꢓ ꢒꢕꢐ ꢑꢁꢔꢎ ꢉ ꢖ ꢄꢓꢐ ꢀ  
SDAS111B − APRIL 1982 − REVISED DECEMBER 1994  
SN54ALS02A, SN54AS02 . . . J PACKAGE  
SN74ALS02A, SN74AS02 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs  
1Y  
1A  
1B  
2Y  
2A  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
4Y  
4B  
4A  
3Y  
3B  
3A  
description  
These devices contain four independent 2-input  
positive-NOR gates. They perform the Boolean  
functions Y = A + B or Y = A B in positive logic.  
2B  
GND  
8
The SN54ALS02A and SN54AS02 are  
characterized for operation over the full military  
temperature range of 55°C to 125°C. The  
SN74ALS02A and SN74AS02 are characterized  
for operation from 0°C to 70°C.  
SN54ALS02A, SN54AS02 . . . FK PACKAGE  
(TOP VIEW)  
FUNCTION TABLE  
(each gate)  
3
2
1
20 19  
18  
1B  
NC  
2Y  
4B  
NC  
4A  
NC  
3Y  
4
5
6
7
8
INPUTS  
OUTPUT  
Y
17  
16  
15  
14  
A
B
X
H
L
H
X
L
L
L
NC  
2A  
9 10 11 12 13  
H
NC − No internal connection  
logic symbol  
logic diagram (positive logic)  
2
1A  
3
2
1A  
3
1
4
1  
1
4
1Y  
2Y  
3Y  
4Y  
1Y  
2Y  
3Y  
4Y  
1B  
5
1B  
5
2A  
6
2A  
6
2B  
8
2B  
8
3A  
9
10  
13  
3A  
9
10  
13  
3B  
11  
3B  
11  
4A  
12  
4B  
4A  
12  
4B  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
ꢏꢎ ꢔ ꢍꢌ ꢘ ꢓꢒ ꢔꢁ ꢍ ꢄꢓꢄ ꢙꢚ ꢛ ꢜꢝ ꢞꢟ ꢠꢙꢜ ꢚ ꢙꢡ ꢢꢣ ꢝ ꢝ ꢤꢚꢠ ꢟꢡ ꢜꢛ ꢥꢣꢦ ꢧꢙꢢ ꢟꢠ ꢙꢜꢚ ꢨꢟ ꢠꢤ ꢩ  
ꢏꢝ ꢜ ꢨꢣꢢ ꢠ ꢡ ꢢ ꢜꢚ ꢛꢜ ꢝ ꢞ ꢠ ꢜ ꢡ ꢥꢤ ꢢ ꢙꢛ ꢙꢢꢟ ꢠꢙ ꢜꢚꢡ ꢥꢤ ꢝ ꢠꢪ ꢤ ꢠꢤ ꢝ ꢞꢡ ꢜꢛ ꢓꢤꢫ ꢟꢡ ꢒꢚꢡ ꢠꢝ ꢣꢞ ꢤꢚꢠ ꢡ  
ꢡ ꢠ ꢟ ꢚꢨ ꢟ ꢝꢨ ꢬ ꢟ ꢝꢝ ꢟ ꢚ ꢠꢭꢩ ꢏꢝ ꢜ ꢨꢣꢢ ꢠꢙꢜꢚ ꢥꢝ ꢜꢢ ꢤꢡ ꢡꢙ ꢚꢮ ꢨꢜꢤ ꢡ ꢚꢜꢠ ꢚꢤ ꢢꢤ ꢡꢡ ꢟꢝ ꢙꢧ ꢭ ꢙꢚꢢ ꢧꢣꢨ ꢤ  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
Copyright 1994, Texas Instruments Incorporated  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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