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SN74ALS01N-10 PDF预览

SN74ALS01N-10

更新时间: 2024-11-04 15:52:07
品牌 Logo 应用领域
德州仪器 - TI 输入元件光电二极管逻辑集成电路
页数 文件大小 规格书
3页 50K
描述
ALS SERIES, QUAD 2-INPUT NAND GATE, PDIP14

SN74ALS01N-10 技术参数

生命周期:Obsolete包装说明:DIP,
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.82Is Samacsys:N
系列:ALSJESD-30 代码:R-PDIP-T14
长度:19.305 mm负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE功能数量:4
输入次数:2端子数量:14
最高工作温度:70 °C最低工作温度:
输出特性:OPEN-COLLECTOR封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE最大电源电流(ICC):3 mA
传播延迟(tpd):28 ns认证状态:Not Qualified
座面最大高度:5.08 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

SN74ALS01N-10 数据手册

 浏览型号SN74ALS01N-10的Datasheet PDF文件第2页浏览型号SN74ALS01N-10的Datasheet PDF文件第3页 
ꢋ ꢌꢄꢍꢎ ꢌꢏꢅ ꢐꢉ ꢑꢒꢓ ꢁꢏ ꢌꢔ ꢉꢏꢕ ꢀ ꢓꢔ ꢓꢖꢐ ꢒꢁꢄꢁꢍ ꢉ ꢗꢄꢔꢐ  
SDAS188 − D2661, APRIL 1982 − REVISED MAY 1986  
Package Options Include Plastic Small  
Outline Packages, Ceramic Chip Carriers,  
and Standard Plastic and Ceramic 300-mil  
DIPs  
SN54ALS01 . . . J PACKAGE  
SN74ALS01 . . . D OR N PACKAGE  
(TOP VIEW)  
Dependable Texas Instruments Quality and  
V
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1Y  
1A  
1B  
2Y  
2A  
CC  
Reliability  
4Y  
4B  
4A  
3Y  
3B  
3A  
description  
These devices contain four independent 2-input  
NAND gates. They perform the Boolean functions  
Y = AB or Y = A+B in positive logic. The  
open-collector outputs require pullup resistors to  
perform correctly. They may be connected to other  
open-collector outputs to implement active-low  
wired-OR or active-high wired-AND functions.  
Open-collector devices are often used to generate  
2B  
GND  
8
SN54ALS01 . . . FK PACKAGE  
(TOP VIEW)  
higher V  
levels.  
OH  
3
2
1
20 19  
18  
The SN54ALS01 is characterized for operation  
over the full military temperature range of 55°C  
to 125°C. The SN74ALS01 is characterized for  
operation from 0°C to 70°C.  
4B  
NC  
4A  
NC  
3Y  
1B  
4
5
6
7
8
NC  
2Y  
NC  
2A  
17  
16  
15  
14  
FUNCTION TABLE  
(each gate)  
9 10 11 12 13  
INPUTS  
OUTPUT  
A
H
L
B
H
X
L
Y
L
H
H
NCNo internal connection  
X
logic diagram (positive logic)  
logic symbol  
1A  
2
1Y  
&
1A  
1
4
1B  
1Y  
2Y  
3
1B  
5
2A  
2B  
2A  
2Y  
6
2B  
8
3A  
10  
13  
3A  
3B  
3Y  
4Y  
9
3Y  
4Y  
3B  
11  
4A  
4B  
12  
4A  
4B  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Pin numbers shown are for D, J, and N packages.  
Copyright 1986, Texas Instruments Incorporated  
5BASIC  
ꢣ ꢧ ꢤ ꢣꢜ ꢝꢱ ꢟꢞ ꢢ ꢪꢪ ꢨꢢ ꢠ ꢢ ꢡ ꢧ ꢣ ꢧ ꢠ ꢤ ꢬ  
ꢣꢰ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77001  

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