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SN74AHCT573DBR PDF预览

SN74AHCT573DBR

更新时间： 2024-09-13 05:24:55
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
17页 546K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SN74AHCT573DBR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SSOP
包装说明：SSOP, SSOP20,.3针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.4其他特性：BROADSIDE VERSION OF 373
控制类型：ENABLE LOW计数方向：UNIDIRECTIONAL
系列：AHCT/VHCT/VTJESD-30 代码：R-PDSO-G20
JESD-609代码：e4长度：7.2 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.008 A湿度敏感等级：1
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP20,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：5 V
最大电源电流（ICC）：0.04 mAProp。Delay @ Nom-Sup：10 ns
传播延迟（tpd）：10 ns认证状态：Not Qualified
座面最大高度：2 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：5.3 mm
Base Number Matches：1

SN74AHCT573DBR 数据手册

 浏览型号SN74AHCT573DBR的Datasheet PDF文件第2页浏览型号SN74AHCT573DBR的Datasheet PDF文件第3页浏览型号SN74AHCT573DBR的Datasheet PDF文件第4页浏览型号SN74AHCT573DBR的Datasheet PDF文件第5页浏览型号SN74AHCT573DBR的Datasheet PDF文件第6页浏览型号SN74AHCT573DBR的Datasheet PDF文件第7页 
SN54AHCT573, SN74AHCT573  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCLS243N – OCTOBER 1995 – REVISED JULY 2003  
SN54AHCT573 . . . J OR W PACKAGE  
SN74AHCT573 . . . DB, DGV, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
LE  
– 1000-V Charged-Device Model (C101)  
description/ordering information  
The ’AHCT573 devices are octal transparent  
D-type latches. When the latch-enable (LE) input  
is high, the Q outputs follow the data (D) inputs.  
When LE is low, the Q outputs are latched at the  
logic levels of the D inputs.  
GND  
SN54AHCT573 . . . FK PACKAGE  
(TOP VIEW)  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low) or the high-impedance state. In  
the high-impedance state, the outputs neither  
load nor drive the bus lines significantly. The  
high-impedance state and increased drive  
provide the capability to drive bus lines without  
interface or pullup components.  
3
2
1 20 19  
18  
2Q  
3Q  
4Q  
5Q  
6Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
15  
14  
To ensure the high-impedance state during power  
9 10 11 12 13  
up or power down, OE should be tied to V  
CC  
through a pullup resistor; the minimum value of  
the resistor is determined by the current-sinking  
capability of the driver.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
Tube  
SN74AHCT573N  
SN74AHCT573N  
Tube  
SN74AHCT573DW  
SN74AHCT573DWR  
SN74AHCT573NSR  
SN74AHCT573DBR  
SN74AHCT573PW  
SN74AHCT573PWR  
SOIC – DW  
AHCT573  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP – NS  
AHCT573  
HB573  
–40°C to 85°C  
SSOP – DB  
TSSOP – PW  
HB573  
Tape and reel  
Tape and reel  
Tube  
TVSOP – DGV  
CDIP – J  
SN74AHCT573DGVR HB573  
SNJ54AHCT573J  
SNJ54AHCT573W  
SNJ54AHCT573FK  
SNJ54AHCT573J  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54AHCT573W  
SNJ54AHCT573FK  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...17

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SN74AHCT573DBR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AHCT573NE4 TI

完全替代

 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74AHCT573DBRE4 TI

完全替代

 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74AHCT573DBLE TI

完全替代

 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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