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SN74AHCT573

更新时间: 2024-09-14 23:09:43
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OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN74AHCT573 数据手册

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SN54AHCT573, SN74AHCT573  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCLS243L – OCTOBER 1995 – REVISED JANUARY 2000  
SN54AHCT573 . . . J OR W PACKAGE  
SN74AHCT573 . . . DB, DGV, DW, N, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
Inputs Are TTL-Voltage Compatible  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
14  
13  
12  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Very Small-Outline (DGV), Thin  
Shrink Small-Outline (PW), and Ceramic  
Flat (W) Packages, Ceramic Chip Carriers  
(FK), and Standard Plastic (N) and Ceramic  
(J) DIPs  
GND 10  
11 LE  
description  
SN54AHCT573 . . . FK PACKAGE  
(TOP VIEW)  
The ’AHCT573 devices are octal transparent  
D-type latches. When the latch-enable (LE) input  
is high, the Q outputs follow the data (D) inputs.  
When LE is low, the Q outputs are latched at the  
logic levels of the D inputs.  
3
2
1 20 19  
18  
2Q  
3Q  
4Q  
5Q  
6Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low) or the high-impedance state. In  
the high-impedance state, the outputs neither  
load nor drive the bus lines significantly. The  
high-impedance state and increased drive  
provide the capability to drive bus lines without  
interface or pullup components.  
17  
16  
15  
14  
9 10 11 12 13  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
The SN54AHCT573 is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74AHCT573 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each latch)  
INPUTS  
OUTPUT  
Q
OE  
L
LE  
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 2000, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74AHCT573 替代型号

型号 品牌 替代类型 描述 数据表
SN54AHCT573 TI

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