5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SN74AHCT374DGV
SN74AHCT374DGV PDF预览

SN74AHCT374DGV

更新时间： 2024-10-30 23:09:43
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路电视光电二极管输出元件
页数 文件大小 规格书
17页 555K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SN74AHCT374DGV 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：PLASTIC, TVSOP-20针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.15Is Samacsys：N
系列：AHCT/VHCTJESD-30 代码：R-PDSO-G20
长度：5 mm逻辑集成电路类型：BUS DRIVER
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP20,.25,16封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟（tpd）：11.5 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.4 mm
端子位置：DUAL宽度：4.4 mm
Base Number Matches：1

SN74AHCT374DGV 数据手册

 浏览型号SN74AHCT374DGV的Datasheet PDF文件第2页浏览型号SN74AHCT374DGV的Datasheet PDF文件第3页浏览型号SN74AHCT374DGV的Datasheet PDF文件第4页浏览型号SN74AHCT374DGV的Datasheet PDF文件第5页浏览型号SN74AHCT374DGV的Datasheet PDF文件第6页浏览型号SN74AHCT374DGV的Datasheet PDF文件第7页 
SN54AHCT374, SN74AHCT374  
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
SCLS241L – OCTOBER 1995 – REVISED JULY 2003  
Inputs Are TTL-Voltage Compatible  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
– 1000-V Charged-Device Model (C101)  
SN54AHCT374 . . . J OR W PACKAGE  
SN74AHCT374 . . . DB, DGV, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
SN54AHCT374 . . . FK PACKAGE  
(TOP VIEW)  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
1
2
3
4
5
6
7
8
9
20  
19  
18  
3
2
1
20 19  
18  
8D  
7D  
7Q  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
17  
16  
17 7D  
16 7Q  
15 6Q  
14 6D  
13 5D  
12 5Q  
11 CLK  
15 6Q  
14  
9 10 11 12 13  
6D  
GND 10  
description/ordering information  
The ’AHCT374 devices are octal edge-triggered D-type flip-flops that feature 3-state outputs designed  
specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable  
for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.  
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels of the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus  
lines without interface or pullup components.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
Tube  
SN74AHCT374N  
SN74AHCT374N  
Tube  
SN74AHCT374DW  
SN74AHCT374DWR  
SN74AHCT374NSR  
SN74AHCT374DBR  
SN74AHCT374PW  
SN74AHCT374PWR  
SOIC – DW  
AHCT374  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP – NS  
AHCT374  
HB374  
–40°C to 85°C  
SSOP – DB  
TSSOP – PW  
HB374  
Tape and reel  
Tape and reel  
Tube  
TVSOP – DGV  
CDIP – J  
SN74AHCT374DGVR HB374  
SNJ54AHCT374J  
SNJ54AHCT374W  
SNJ54AHCT374FK  
SNJ54AHCT374J  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54AHCT374W  
SNJ54AHCT374FK  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...17

中文翻译

下载PDF

与SN74AHCT374DGV相关器件

型号 品牌 获取价格 描述 数据表
SN74AHCT374DGVR TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74AHCT374DGVRE4 TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74AHCT374DGVRG4 TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74AHCT374DW TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74AHCT374DWE4 TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74AHCT374DWG4 TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74AHCT374DWR TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74AHCT374DWRE4 TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74AHCT374DWRG4 TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74AHCT374N TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

与SN74AHCT374DGV相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证