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SN74AHCT373N PDF预览

SN74AHCT373N

更新时间： 2024-11-29 23:09:43
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管输出元件PC
页数 文件大小 规格书
16页 532K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SN74AHCT373N 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：DIP
包装说明：DIP-20针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.1Samacsys Confidence：
Samacsys Status：ReleasedSamacsys PartID：604672
Samacsys Pin Count：20Samacsys Part Category：Integrated Circuit
Samacsys Package Category：OtherSamacsys Footprint Name：DIP254P762X508-20
Samacsys Released Date：2017-01-12 12:59:53Is Samacsys：N
控制类型：ENABLE LOW计数方向：UNIDIRECTIONAL
系列：AHCT/VHCT/VTJESD-30 代码：R-PDIP-T20
JESD-609代码：e4长度：25.4 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.008 A位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP20,.3
封装形状：RECTANGULAR封装形式：IN-LINE
包装方法：TUBE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V最大电源电流（ICC）：0.04 mA
Prop。Delay @ Nom-Sup：10.5 ns传播延迟（tpd）：14.5 ns
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmBase Number Matches：1

SN74AHCT373N 数据手册

 浏览型号SN74AHCT373N的Datasheet PDF文件第2页浏览型号SN74AHCT373N的Datasheet PDF文件第3页浏览型号SN74AHCT373N的Datasheet PDF文件第4页浏览型号SN74AHCT373N的Datasheet PDF文件第5页浏览型号SN74AHCT373N的Datasheet PDF文件第6页浏览型号SN74AHCT373N的Datasheet PDF文件第7页 
SN54AHCT373, SN74AHCT373  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCLS239M – OCTOBER 1995 – REVISED JULY 2003  
Inputs Are TTL-Voltage Compatible  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
– 1000-V Charged-Device Model (C101)  
SN54AHCT373 . . . J OR W PACKAGE  
SN74AHCT373 . . . DB, DGV, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
SN54AHCT373 . . . FK PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
3
2
1 20 19  
18  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
LE  
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
4
5
6
7
8
17  
16  
15  
14 6D  
9 10 11 12 13  
GND  
description/ordering information  
The ’AHCT373 devices are octal-transparent D-type latches. When the latch-enable (LE) input is high, the Q  
outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines  
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without  
interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
Tube  
SN74AHCT373N  
SN74AHCT373N  
Tube  
SN74AHCT373DW  
SN74AHCT373DWR  
SN74AHCT373NSR  
SN74AHCT373DBR  
SN74AHCT373PW  
SN74AHCT373PWR  
SOIC – DW  
AHCT373  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP – NS  
AHCT373  
HB373  
–40°C to 85°C  
SSOP – DB  
TSSOP – PW  
HB373  
Tape and reel  
Tape and reel  
Tube  
TVSOP – DGV  
CDIP – J  
SN74AHCT373DGVR HB373  
SNJ54AHCT373J  
SNJ54AHCT373W  
SNJ54AHCT373FK  
SNJ54AHCT373J  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54AHCT373W  
SNJ54AHCT373FK  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...16

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SN74AHCT373N 替代型号

型号 品牌 替代类型 描述 数据表
SN74AHCT373NE4 TI

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 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SNJ54AHCT373J TI

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 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
5962-9686701QRA TI

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 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SN74AHCT373NSR TI

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SN74AHCT373NSRE4 TI

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SN74AHCT373NSRG4 TI

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SN74AHCT373PW TI

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SN74AHCT373PWE4 TI

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SN74AHCT373PWG4 TI

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 		OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74AHCT373PWLE TI

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 		OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74AHCT373PWR TI

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 		OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74AHCT373PWRE4 TI

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 		OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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