ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢊ ꢀꢁꢋ ꢃꢄ ꢅꢆ ꢇꢈ ꢉ
ꢍꢄꢎꢏ ꢍꢐꢑ ꢒ ꢉ ꢓꢔꢁ ꢐꢍꢇ ꢐꢕ ꢀꢔ ꢇ ꢔꢖꢒ ꢓꢕꢏ ꢗ ꢄꢇꢒ ꢀ
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SCLS248L − OCTOBER 1995 − REVISED JULY 2003
D
D
Inputs Are TTL-Voltage Compatible
D
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
SN54AHCT32 . . . J OR W PACKAGE
SN74AHCT32 . . . D, DB, DGV, N, NS,
OR PW PACKAGE
SN74AHCT32 . . . RGY PACKAGE
(TOP VIEW)
SN54AHCT32 . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
1
14
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
1Y
2A
2B
V
CC
3
2
1
20 19
18
4A
NC
4Y
1Y
NC
2A
4
5
6
7
8
1B
1Y
2A
2B
2Y
13 4B
12 4A
2
3
4
5
6
4B
4A
4Y
3B
3A
3Y
17
16
11
10
9
4Y
3B
3A
15 NC
14
9 10 11 12 13
NC
2B
3B
2Y
GND
7
8
8
NC − No internal connection
description/ordering information
The ’AHCT32 devices are quadruple 2-input positive-OR gates. These devices perform the Boolean function
Y + A • B or Y + A ) B in positive logic.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
QFN − RGY
PDIP − N
Tape and reel
Tube
SN74AHCT32RGYR
SN74AHCT32N
HB32
SN74AHCT32N
Tube
SN74AHCT32D
SOIC − D
AHCT32
Tape and reel
Tape and reel
Tape and reel
Tube
SN74AHCT32DR
SN74AHCT32NSR
SN74AHCT32DBR
SN74AHCT32PW
SN74AHCT32PWR
SN74AHCT32DGVR
SNJ54AHCT32J
−40°C to 85°C
SOP − NS
AHCT32
HB32
SSOP − DB
TSSOP − PW
HB32
Tape and reel
Tape and reel
Tube
TVSOP − DGV
CDIP − J
HB32
SNJ54AHCT32J
SNJ54AHCT32W
SNJ54AHCT32FK
CFP − W
Tube
SNJ54AHCT32W
SNJ54AHCT32FK
−55°C to 125°C
LCCC − FK
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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