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SN74AHCT240DGV PDF预览

SN74AHCT240DGV

更新时间： 2024-11-03 23:09:43
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
15页 529K
描述
OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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中文翻译

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SN74AHCT240DGV 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：TSSOP, TSSOP20,.25,16针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.62系列：AHCT/VHCT
JESD-30 代码：R-PDSO-G20长度：5 mm
逻辑集成电路类型：BUS DRIVER位数：4
功能数量：2端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP20,.25,16
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）：9.5 ns认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.4 mm端子位置：DUAL
宽度：4.4 mmBase Number Matches：1

SN74AHCT240DGV 数据手册

 浏览型号SN74AHCT240DGV的Datasheet PDF文件第2页浏览型号SN74AHCT240DGV的Datasheet PDF文件第3页浏览型号SN74AHCT240DGV的Datasheet PDF文件第4页浏览型号SN74AHCT240DGV的Datasheet PDF文件第5页浏览型号SN74AHCT240DGV的Datasheet PDF文件第6页浏览型号SN74AHCT240DGV的Datasheet PDF文件第7页 
SN54AHCT240, SN74AHCT240  
OCTAL BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCLS252K – OCTOBER 1995 – REVISED JULY 2003  
SN54AHCT240 . . . J OR W PACKAGE  
SN74AHCT240 . . . DB, DGV, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
2OE  
1
2
3
4
5
6
7
8
9
10  
20  
19  
description/ordering information  
18 1Y1  
These octal buffers/drivers are designed  
specifically to improve the performance and  
density of 3-state memory-address drivers, clock  
drivers, and bus-oriented receivers and  
transmitters.  
17  
16  
15  
14  
13  
12  
11  
2A4  
1Y2  
2A3  
1Y3  
2A2  
1Y4  
2A1  
The ’AHCT240 devices are organized as two 4-bit  
buffers/line drivers with separate output-enable  
(OE) inputs. When OE is low, the device passes  
data from the A inputs to the Y outputs. When OE  
is high, the outputs are in the high-impedance  
state.  
SN54AHCT240 . . . FK PACKAGE  
(TOP VIEW)  
To ensure the high-impedance state during power  
up or power down, OE should be tied to V  
CC  
3
2
1 20 19  
18  
through a pullup resistor; the minimum value of  
the resistor is determined by the current-sinking  
capability of the driver.  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
1A2  
2Y3  
1A3  
2Y2  
1A4  
4
5
6
7
8
17  
16  
15  
14  
9 10 11 12 13  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
Tube  
SN74AHCT240N  
SN74AHCT240N  
Tube  
SN74AHCT240DW  
SOIC – DW  
AHCT240  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74AHCT240DWR  
SN74AHCT240NSR  
SN74AHCT240DBR  
SN74AHCT240PW  
SN74AHCT240PWR  
SN74AHCT240DGVR  
SNJ54AHCT240J  
SOP – NS  
AHCT240  
HB240  
–40°C to 85°C  
SSOP – DB  
TSSOP – PW  
HB240  
Tape and reel  
Tape and reel  
Tube  
TVSOP – DGV  
CDIP – J  
HB240  
SNJ54AHCT240J  
SNJ54AHCT240W  
SNJ54AHCT240FK  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54AHCT240W  
SNJ54AHCT240FK  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

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