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SN74AHCT240DB PDF预览

SN74AHCT240DB

更新时间： 2024-11-03 23:09:43
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
15页 529K
描述
OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

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SN74AHCT240DB 数据手册

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SN54AHCT240, SN74AHCT240  
OCTAL BUFFERS/DRIVERS  
WITH 3-STATE OUTPUTS  
SCLS252K – OCTOBER 1995 – REVISED JULY 2003  
SN54AHCT240 . . . J OR W PACKAGE  
SN74AHCT240 . . . DB, DGV, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
1OE  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
2OE  
1
2
3
4
5
6
7
8
9
10  
20  
19  
description/ordering information  
18 1Y1  
These octal buffers/drivers are designed  
specifically to improve the performance and  
density of 3-state memory-address drivers, clock  
drivers, and bus-oriented receivers and  
transmitters.  
17  
16  
15  
14  
13  
12  
11  
2A4  
1Y2  
2A3  
1Y3  
2A2  
1Y4  
2A1  
The ’AHCT240 devices are organized as two 4-bit  
buffers/line drivers with separate output-enable  
(OE) inputs. When OE is low, the device passes  
data from the A inputs to the Y outputs. When OE  
is high, the outputs are in the high-impedance  
state.  
SN54AHCT240 . . . FK PACKAGE  
(TOP VIEW)  
To ensure the high-impedance state during power  
up or power down, OE should be tied to V  
CC  
3
2
1 20 19  
18  
through a pullup resistor; the minimum value of  
the resistor is determined by the current-sinking  
capability of the driver.  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
1A2  
2Y3  
1A3  
2Y2  
1A4  
4
5
6
7
8
17  
16  
15  
14  
9 10 11 12 13  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – N  
Tube  
SN74AHCT240N  
SN74AHCT240N  
Tube  
SN74AHCT240DW  
SOIC – DW  
AHCT240  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74AHCT240DWR  
SN74AHCT240NSR  
SN74AHCT240DBR  
SN74AHCT240PW  
SN74AHCT240PWR  
SN74AHCT240DGVR  
SNJ54AHCT240J  
SOP – NS  
AHCT240  
HB240  
–40°C to 85°C  
SSOP – DB  
TSSOP – PW  
HB240  
Tape and reel  
Tape and reel  
Tube  
TVSOP – DGV  
CDIP – J  
HB240  
SNJ54AHCT240J  
SNJ54AHCT240W  
SNJ54AHCT240FK  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54AHCT240W  
SNJ54AHCT240FK  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

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