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SN74AHCT125QPWREP PDF预览

SN74AHCT125QPWREP

更新时间: 2024-11-21 11:58:19
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
12页 556K
描述
QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

SN74AHCT125QPWREP 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:0.87控制类型:ENABLE LOW
计数方向:UNIDIRECTIONAL系列:AHCT/VHCT/VT
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.008 A
湿度敏感等级:1位数:1
功能数量:4端口数量:2
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TR峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):0.02 mA
Prop。Delay @ Nom-Sup:8.5 ns传播延迟(tpd):8.5 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:4.4 mm
Base Number Matches:1

SN74AHCT125QPWREP 数据手册

 浏览型号SN74AHCT125QPWREP的Datasheet PDF文件第2页浏览型号SN74AHCT125QPWREP的Datasheet PDF文件第3页浏览型号SN74AHCT125QPWREP的Datasheet PDF文件第4页浏览型号SN74AHCT125QPWREP的Datasheet PDF文件第5页浏览型号SN74AHCT125QPWREP的Datasheet PDF文件第6页浏览型号SN74AHCT125QPWREP的Datasheet PDF文件第7页 
ꢎ ꢏꢄꢐꢑ ꢏꢍꢒ ꢌ ꢓꢏꢀ ꢓꢏꢔ ꢔꢌ ꢑ ꢕ ꢄꢇ  
SCLS549 − DECEMBER 2003  
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
D
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
D
D
Extended Temperature Performance of  
−40°C to 125°C  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
Inputs Are TTL-Voltage Compatible  
D OR PW PACKAGE  
(TOP VIEW)  
D
Enhanced Product-Change Notification  
1OE  
1A  
1
2
3
4
5
6
7
V
CC  
13 4OE  
14  
D
Qualification Pedigree  
12  
11  
10  
9
1Y  
4A  
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
2OE  
2A  
4Y  
3OE  
3A  
2Y  
8
GND  
3Y  
description/ordering information  
The SN74AHCT125 is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each  
output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate  
passes the data from the A input to its Y output.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
SOIC − D  
Tape and reel  
Tape and reel  
SN74AHCT125QDREP  
AHCT125QEP  
−40°C to 125°C  
TSSOP − PW  
SN74AHCT125QPWREP HB125EP  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
FUNCTION TABLE  
(each buffer)  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
H
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢇꢥ  
Copyright 2003, Texas Instruments Incorporated  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74AHCT125QPWREP 替代型号

型号 品牌 替代类型 描述 数据表
SN74AHCT125QPWRQ1 TI

完全替代

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
V62/04683-01YE TI

完全替代

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
74AHCT126T14-13 DIODES

类似代替

QUADRUPLE 3-STATE BUFFERS OE HIGH

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