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SN74AHCT02DGV

更新时间： 2024-11-26 22:40:23
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德州仪器 - TI 输入元件
页数 文件大小 规格书
6页 86K
描述
QUADRUPLE 2-INPUT POSITIVE-NOR GATES

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SN74AHCT02DGV 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：TSSOP, TSSOP14,.25针数：14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.56系列：AHCT/VHCT
JESD-30 代码：R-PDSO-G14长度：4.4 mm
逻辑集成电路类型：NOR GATE功能数量：4
输入次数：2端子数量：14
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP14,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟（tpd）：8.5 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.4 mm
端子位置：DUAL宽度：3.6 mm
Base Number Matches：1

SN74AHCT02DGV 数据手册

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SN54AHCT02, SN74AHCT02  
QUADRUPLE 2-INPUT POSITIVE-NOR GATES  
SCLS262I – DECEMBER 1995 – REVISED JANUARY 2000  
SN54AHCT02 . . . J OR W PACKAGE  
SN74AHCT02 . . . D, DB, DGV, N, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
Inputs Are TTL-Voltage Compatible  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
1Y  
1A  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
4Y  
4B  
4A  
1B  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
2Y  
2A  
10 3Y  
9
8
2B  
3B  
3A  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), Thin Very Small-Outline (DGV), Thin  
Shrink Small-Outline (PW), and Ceramic  
Flat (W) Packages, Ceramic Chip Carriers  
(FK), and Standard Plastic (N) and Ceramic  
(J) DIPs  
GND  
SN54AHCT02 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1 20 19  
18  
description  
4B  
NC  
4A  
1B  
NC  
2Y  
4
5
6
7
8
17  
16  
These devices contain four independent 2-input  
NOR gates that perform the Boolean function  
Y = A B or Y = A + B in positive logic.  
15 NC  
14  
9 10 11 12 13  
NC  
2A  
3Y  
The SN54AHCT02 is characterized for operation  
over the full military temperature range of –55°C  
to 125°C. The SN74AHCT02 is characterized for  
operation from –40°C to 85°C.  
NC – No internal connection  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
B
X
H
L
H
X
L
L
L
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 2000, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
123456

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