ꢀꢁꢂ ꢃ ꢄ ꢅꢆ ꢇꢈ ꢈꢉ ꢊꢋ
ꢌ ꢍꢄꢎꢏ ꢍꢋꢐ ꢊ ꢑ ꢉꢒꢁ ꢋꢍꢇ ꢋꢓ ꢀꢒ ꢇ ꢒꢔꢊ ꢉꢁꢄꢁꢎ ꢕ ꢄꢇꢊ ꢀ
SCLS507 − JUNE 2003
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
D
D
Extended Temperature Performance of
−55°C to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
D OR PW PACKAGE
(TOP VIEW)
D
D
D
Enhanced Product-Change Notification
†
1A
1B
V
CC
Qualification Pedigree
1
2
3
4
5
6
7
14
13
12
11
4B
4A
4Y
Inputs Are TTL-Voltage Compatible
1Y
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification testing
should not be viewed as justifying use of this component beyond
specified performance and environmental limits.
2A
2B
10 3B
9
8
2Y
3A
3Y
GND
description/ordering information
The ’AHCT00 device performs the Boolean function Y = A • B or Y = A + B in positive logic.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
PACKAGE
T
A
SOIC − D
Tape and reel
Tape and reel
SN74AHCT00MDREP
SN74AHCT00MPWREP
AHCT00MEP
AHT00EP
−55°C to 125°C
TSSOP − PW
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
B
H
X
L
H
L
L
H
H
X
logic diagram, each gate (positive logic)
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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