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SN74AHC573DWR PDF预览

SN74AHC573DWR

更新时间: 2024-11-04 23:06:15
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管输出元件PC
页数 文件大小 规格书
18页 575K
描述
OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS

SN74AHC573DWR 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP20,.4针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:0.7Samacsys Confidence:3
Samacsys Status:ReleasedSamacsys PartID:745854
Samacsys Pin Count:20Samacsys Part Category:Integrated Circuit
Samacsys Package Category:Small Outline PackagesSamacsys Footprint Name:SN74AHC573DWR-1
Samacsys Released Date:2019-01-28 14:36:30Is Samacsys:N
其他特性:BROADSIDE VERSION OF 373控制类型:ENABLE LOW
计数方向:UNIDIRECTIONAL系列:AHC/VHC/H/U/V
JESD-30 代码:R-PDSO-G20JESD-609代码:e4
长度:12.8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.008 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TR峰值回流温度(摄氏度):260
电源:2/5.5 V最大电源电流(ICC):0.04 mA
Prop。Delay @ Nom-Sup:10 ns传播延迟(tpd):16.5 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

SN74AHC573DWR 数据手册

 浏览型号SN74AHC573DWR的Datasheet PDF文件第2页浏览型号SN74AHC573DWR的Datasheet PDF文件第3页浏览型号SN74AHC573DWR的Datasheet PDF文件第4页浏览型号SN74AHC573DWR的Datasheet PDF文件第5页浏览型号SN74AHC573DWR的Datasheet PDF文件第6页浏览型号SN74AHC573DWR的Datasheet PDF文件第7页 
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SCLS242K − OCTOBER 1995 − REVISED JANUARY 2004  
SN54AHC573 . . . J OR W PACKAGE  
SN74AHC573 . . . DB, DGV, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
Operating Range 2-V to 5.5-V V  
CC  
3-State Outputs Directly Drive Bus Lines  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
14  
13  
12  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
description/ordering information  
The ’AHC573 devices are octal transparent  
D-type latches designed for 2-V to 5.5-V V  
operation.  
CC  
When the latch-enable (LE) input is high, the  
Q outputs follow the data (D) inputs. When LE is  
low, the Q outputs are latched at the logic levels  
of the D inputs.  
GND 10  
11 LE  
SN54AHC573 . . . FK PACKAGE  
(TOP VIEW)  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low) or the high-impedance state. In  
the high-impedance state, the outputs neither  
load nor drive the bus lines significantly. The  
high-impedance state and increased drive  
provide the capability to drive bus lines without  
interface or pullup components.  
3
2
1 20 19  
18  
2Q  
3Q  
4Q  
5Q  
6Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
15  
14  
OE does not affect the internal operations of the  
latches. Old data can be retained or new data can  
be entered while the outputs are in the  
high-impedance state.  
9 10 11 12 13  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
Tube  
SN74AHC573N  
SN74AHC573N  
Tube  
SN74AHC573DW  
SN74AHC573DWR  
SN74AHC573NSR  
SN74AHC573DBR  
SN74AHC573PW  
SN74AHC573PWR  
SN74AHC573DGVR  
SNJ54AHC573J  
SOIC − DW  
AHC573  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
AHC573  
HA573  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
HA573  
Tape and reel  
Tape and reel  
Tube  
TVSOP − DGV  
CDIP − J  
HA573  
SNJ54AHC573J  
SNJ54AHC573W  
SNJ54AHC573FK  
CFP − W  
Tube  
SNJ54AHC573W  
SNJ54AHC573FK  
−55°C to 125°C  
LCCC − FK  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2004, Texas Instruments Incorporated  
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ꢠ ꢗꢤ ꢡꢞꢞ ꢙ ꢝꢧꢡ ꢚ ꢩꢖ ꢞꢡ ꢗ ꢙꢝꢡ ꢥꢦ ꢊ ꢗ ꢜꢤ ꢤ ꢙ ꢝꢧꢡ ꢚ ꢢꢚ ꢙ ꢥꢠꢟ ꢝꢞ ꢉ ꢢꢚ ꢙ ꢥꢠꢟ ꢝꢖꢙ ꢗ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74AHC573DWR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AHC573DWE4 TI

完全替代

OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
SN74AHC573DW TI

完全替代

OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS

与SN74AHC573DWR相关器件

型号 品牌 获取价格 描述 数据表
SN74AHC573DWRE4 TI

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OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
SN74AHC573DWRG4 TI

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具有三态输出的八路透明 D 型锁存器 | DW | 20 | -40 to 125
SN74AHC573N TI

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OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
SN74AHC573NE4 TI

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OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
SN74AHC573NSR TI

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OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
SN74AHC573NSRE4 TI

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OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
SN74AHC573NSRG4 TI

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Octal Transparent D-Type Latches With 3-State Outputs 20-SO -40 to 85
SN74AHC573PW TI

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OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
SN74AHC573PWE4 TI

获取价格

OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
SN74AHC573PWLE TI

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OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS