5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SN74AHC573DGV
SN74AHC573DGV PDF预览

SN74AHC573DGV

更新时间： 2024-11-05 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
18页 568K
描述
AHC SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, TVSOP-20

阅读下载

中文翻译

获取价格

SN74AHC573DGV 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：TVSOP-20针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.51Is Samacsys：N
系列：AHCJESD-30 代码：R-PDSO-G20
长度：5 mm逻辑集成电路类型：BUS DRIVER
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP20,.25,16封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH传播延迟（tpd）：17.5 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.4 mm
端子位置：DUAL宽度：4.4 mm
Base Number Matches：1

SN74AHC573DGV 数据手册

 浏览型号SN74AHC573DGV的Datasheet PDF文件第2页浏览型号SN74AHC573DGV的Datasheet PDF文件第3页浏览型号SN74AHC573DGV的Datasheet PDF文件第4页浏览型号SN74AHC573DGV的Datasheet PDF文件第5页浏览型号SN74AHC573DGV的Datasheet PDF文件第6页浏览型号SN74AHC573DGV的Datasheet PDF文件第7页 
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢂ
ꢇ
ꢈ
ꢉ
ꢀ
ꢁ
ꢇ
ꢃ
ꢊ ꢆꢋꢄꢌ ꢋ ꢍꢄꢁꢀ ꢎꢄꢍꢏ ꢁꢋ ꢐꢑꢋ ꢒꢎ ꢏ ꢌꢄꢋꢆ ꢅ ꢏ  
ꢄ
ꢅ
ꢆ
ꢂ
ꢇ
ꢈ
ꢀ
ꢀ
ꢓ
ꢔ
ꢋ
ꢅ
ꢈ
ꢑ
ꢀ
ꢋ
ꢄ
ꢋ
ꢏ
ꢊ
ꢕ
ꢋ
ꢎ
ꢕ
ꢋ
SCLS242K − OCTOBER 1995 − REVISED JANUARY 2004  
SN54AHC573 . . . J OR W PACKAGE  
SN74AHC573 . . . DB, DGV, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
Operating Range 2-V to 5.5-V V  
CC  
3-State Outputs Directly Drive Bus Lines  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
14  
13  
12  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
description/ordering information  
The ’AHC573 devices are octal transparent  
D-type latches designed for 2-V to 5.5-V V  
operation.  
CC  
When the latch-enable (LE) input is high, the  
Q outputs follow the data (D) inputs. When LE is  
low, the Q outputs are latched at the logic levels  
of the D inputs.  
GND 10  
11 LE  
SN54AHC573 . . . FK PACKAGE  
(TOP VIEW)  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low) or the high-impedance state. In  
the high-impedance state, the outputs neither  
load nor drive the bus lines significantly. The  
high-impedance state and increased drive  
provide the capability to drive bus lines without  
interface or pullup components.  
3
2
1 20 19  
18  
2Q  
3Q  
4Q  
5Q  
6Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
15  
14  
OE does not affect the internal operations of the  
latches. Old data can be retained or new data can  
be entered while the outputs are in the  
high-impedance state.  
9 10 11 12 13  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − N  
Tube  
SN74AHC573N  
SN74AHC573N  
Tube  
SN74AHC573DW  
SN74AHC573DWR  
SN74AHC573NSR  
SN74AHC573DBR  
SN74AHC573PW  
SN74AHC573PWR  
SN74AHC573DGVR  
SNJ54AHC573J  
SOIC − DW  
AHC573  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SOP − NS  
AHC573  
HA573  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
HA573  
Tape and reel  
Tape and reel  
Tube  
TVSOP − DGV  
CDIP − J  
HA573  
SNJ54AHC573J  
SNJ54AHC573W  
SNJ54AHC573FK  
CFP − W  
Tube  
SNJ54AHC573W  
SNJ54AHC573FK  
−55°C to 125°C  
LCCC − FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢎ
ꢎ
ꢍ
ꢊ
ꢥ
ꢐ
ꢠ
ꢜ
ꢕ
ꢆ
ꢞ
ꢋ
ꢟ
ꢩ
ꢔ
ꢙ
ꢊ
ꢗ
ꢚ
ꢁ
ꢘ
ꢐ
ꢄ
ꢋ
ꢄ
ꢖ
ꢗ
ꢡ
ꢠ
ꢘ
ꢙ
ꢟ
ꢟ
ꢚ
ꢛ
ꢜ
ꢜ
ꢗ
ꢝ
ꢝ
ꢖ
ꢖ
ꢢ
ꢙ
ꢙ
ꢚ
ꢗ
ꢗ
ꢙ
ꢖ
ꢞ
ꢞ
ꢢ
ꢞ
ꢟ
ꢠ
ꢚ
ꢚ
ꢡ
ꢡ
ꢗ
ꢝ
ꢜ
ꢛ
ꢞ
ꢞ
ꢞ
ꢗ
ꢙ
ꢘ
ꢢ
ꢠ
ꢣ
ꢞ
ꢞ
ꢤ
ꢖ
ꢟ
ꢜ
ꢞ
ꢝ
ꢖ
ꢝ
ꢪ
ꢙ
ꢚ
ꢗ
ꢠ
ꢥ
ꢜ
ꢗ
ꢥ
ꢝ
ꢝ
ꢡ
ꢞ
ꢡ
ꢦ
Copyright 2004, Texas Instruments Incorporated  
ꢊ ꢗ ꢢ ꢚ ꢙꢥ ꢠꢟ ꢝꢞ ꢟꢙ ꢛꢢ ꢤꢖ ꢜꢗ ꢝ ꢝꢙ ꢬꢔ ꢌꢑ ꢎꢍ ꢭ ꢑꢈꢮꢂ ꢈꢂꢉ ꢜꢤꢤ ꢢꢜ ꢚ ꢜ ꢛꢡ ꢝꢡꢚ ꢞ ꢜ ꢚ ꢡ ꢝꢡ ꢞꢝꢡ ꢥ  
ꢚ
ꢙ
ꢟ
ꢝ
ꢙ
ꢚ
ꢛ
ꢝ
ꢙ
ꢞ
ꢢ
ꢖ
ꢘ
ꢖ
ꢟ
ꢡ
ꢚ
ꢝ
ꢧ
ꢝ
ꢡ
ꢚ
ꢙ
ꢘ
ꢋ
ꢡ
ꢨ
ꢜ
ꢔ
ꢗ
ꢛ
ꢡ
ꢞ
ꢝ
ꢜ
ꢗ
ꢥ
ꢚ
ꢥ
ꢜ
ꢝ ꢡ ꢞ ꢝꢖ ꢗꢫ ꢙꢘ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ  
ꢚ
ꢜ
ꢗ
ꢝ
ꢪ
ꢦ
ꢎ
ꢚ
ꢙ
ꢥ
ꢝ
ꢖ
ꢙ
ꢟ
ꢡ
ꢞ
ꢖ
ꢗ
ꢫ
ꢥ
ꢙ
ꢡ
ꢙ
ꢝ
ꢗ
ꢡ
ꢟ
ꢡ
ꢞ
ꢜ
ꢚ
ꢖ
ꢤ
ꢖ
ꢗ
ꢟ
ꢤ
ꢠ
ꢠ ꢗꢤ ꢡꢞꢞ ꢙ ꢝꢧꢡ ꢚ ꢩꢖ ꢞꢡ ꢗ ꢙꢝꢡ ꢥꢦ ꢊ ꢗ ꢜꢤ ꢤ ꢙ ꢝꢧꢡ ꢚ ꢢꢚ ꢙ ꢥꢠꢟ ꢝꢞ ꢉ ꢢꢚ ꢙ ꢥꢠꢟ ꢝꢖꢙ ꢗ  
ꢝ
ꢢ
ꢚ
ꢙ
ꢟ
ꢡ
ꢞ
ꢞ
ꢖ
ꢗ
ꢫ
ꢥ
ꢙ
ꢡ
ꢞ
ꢗ
ꢙ
ꢝ
ꢗ
ꢡ
ꢟ
ꢡ
ꢞ
ꢞ
ꢜ
ꢚ
ꢖ
ꢤ
ꢪ
ꢖ
ꢗ
ꢟ
ꢤ
ꢠ
ꢥ
ꢡ
ꢝ
ꢡ
ꢞ
ꢖ
ꢗ
ꢫ
ꢙ
ꢘ
ꢜ
ꢤ
ꢤ
ꢢ
ꢜ
ꢚ
ꢜ
ꢛ
ꢡ
ꢝ
ꢡ
ꢚ
ꢞ
ꢦ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...18

中文翻译

下载PDF

与SN74AHC573DGV相关器件

型号 品牌 获取价格 描述 数据表
SN74AHC573DGVR TI

获取价格

 		OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
SN74AHC573DGVRE4 TI

获取价格

 		OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
SN74AHC573DGVRG4 TI

获取价格

 		AHC/VHC/H/U/V SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, TVSOP-20
SN74AHC573DW TI

获取价格

 		OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
SN74AHC573DWE4 TI

获取价格

 		OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
SN74AHC573DWR TI

获取价格

 		OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
SN74AHC573DWRE4 TI

获取价格

 		OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
SN74AHC573DWRG4 TI

获取价格

 		具有三态输出的八路透明 D 型锁存器 | DW | 20 | -40 to 125
SN74AHC573N TI

获取价格

 		OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS
SN74AHC573NE4 TI

获取价格

 		OCTAL TRANSPARENT D- TYPE LATCHES WITH 3 STATE OUTPUTS

与SN74AHC573DGV相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证